Pattern collapse, CD (critical dimension) non-uniformity, and poor pattern fidelity induced by the multi-interference effect of DUV process are currently becoming significant issues to an actual process implementation. In the micro- device fabrication of DRAM, capacitor storage node patterning designed with a rectangular shape of sub- quartermicron spacewidth is critically involved in these issues dependent on the process scheme of capacitor formation. In this study, we have evaluated the effect of barrier layers such as thin poly film, inorganic and organic BARC to minimize a thin film multi-interference effect. In addition, illumination source effect during the exposure process and process polarity effect of a positive and negative tone process were also experimented to settle down process control stability.