Throughput in a counterflow pipeline processor

The Counterflow Pipeline Processor, or CFPP, is a unique form of pipelined RISC architecture whose goal is to obtain regular and modular performance from a bi-directional pipeline. In this pipeline, instructions and results move in opposite directions in a counterflow fashion. A basic synchronous model of the CFPP was created and used to study configuration options which affect the flow of instructions and results through the pipeline. These options, which varied instruction execution, pipeline movement arbitration, and result movements, were varied in order to find the configuration which maximized throughput for a set of benchmarks.