Compressed sensing (CS) is being widely used to compress and reconstruct data for processing electrocardiogram (ECG) signals obtained through Wireless Body Area Networks. However, the conventional measurement matrix generator and compression computations for CS are in parallel, resulting in significant power consumption and a large area. This paper proposes a serial measurement matrix generator, which reduces the clock frequencies by using linear feedback shift registers and latches. A CS circuit for ECG signals processing based on the proposed measurement matrix generator is proposed and implemented in a SMIC 55 nm CMOS process. The experimental results show that the power consumption is only 1.690 μW at 1.2 V, and the chip area is 0.608 mm2, which has obvious advantages over the traditional parallel architecture. The reconstruction results show that the Percentage Root-mean-square Difference is 1.32%, which means that the design meets the basic clinical requirements.