Evaluating the safety of self-checking circuits
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[1] Eiji Fujiwara,et al. A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing , 1984, IEEE Transactions on Computers.
[2] Kishor S. Trivedi,et al. Probabilistic modeling of computer system availability , 1987 .
[3] Kishor S. Trivedi,et al. Composite Performance and Dependability Analysis , 1992, Perform. Evaluation.
[4] Edward J. McCluskey,et al. Quantitative Evaluation of Self-Checking Circuits , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[5] Ravishankar K. Iyer,et al. A Statistical Failure/Load Relationship: Results of a Multicomputer Study , 1982, IEEE Transactions on Computers.
[6] Niraj K. Jha,et al. Design and synthesis of self-checking VLSI circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Eiji Fujiwara,et al. A probabilistic measurement for totally self-checking circuits , 1993, Proceedings of 1993 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.
[8] Eiji Fujiwara,et al. A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing , 1987, IEEE Transactions on Computers.
[9] D.P. Siewiorek,et al. A case study of C.mmp, Cm*, and C.vmp: Part I—Experiences with fault tolerance in multiprocessor systems , 1978, Proceedings of the IEEE.
[10] Barry W. Johnson. Design & analysis of fault tolerant digital systems , 1988 .
[11] James E. Smith,et al. Strongly Fault Secure Logic Networks , 1978, IEEE Transactions on Computers.
[12] Gernot Metze,et al. Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes , 1973, IEEE Transactions on Computers.