Simulation and optimization of lightly-doped ultra-thin Triple Metal Double Gate (TM-DG) MOSFET with high-K dielectric for diminished short channel effects

In this paper, we have proposed Lightly-Doped Ultra-Thin Triple Metal Double Gate (TM-DG) MOSFET with High-K Dielectric in the gate oxide to reduce the Short Channel Effects (SCEs). The above device has been optimized with TCAD simulations and it has been found that the TMDG MOSFETs offers better transconductance, subthreshold swing, ON and OFF state currents in nanometer regime than Single Metal DG MOSFETs.

[1]  Tetsu Tanaka,et al.  V/sub th/ fluctuation induced by statistical variation of pocket dopant profile , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[2]  A. Orouji,et al.  Nanoscale Triple Material Double Gate (TM-DG) MOSFET for Improving Short Channel Effects , 2008, 2008 International Conference on Advances in Electronics and Micro-electronics.

[3]  Y. Tosaka,et al.  Analytical surface potential expression for thin-film double-gate SOI MOSFETs , 1994 .

[4]  G. Dewey,et al.  Application of high-κ gate dielectrics and metal gate electrodes to enable silicon and non-silicon logic nanotechnology , 2005 .

[5]  T. Tanaka,et al.  Vth fluctuation induced by statistical variation of pocket dopant profile , 2000 .

[6]  Ken K. Chin,et al.  Dual-material gate (DMG) field effect transistor , 1999 .

[7]  J. Kavalieros,et al.  Gate dielectric scaling for high-performance CMOS: from SiO2 to high-K , 2003, Extended Abstracts of International Workshop on Gate Insulator (IEEE Cat. No.03EX765).

[8]  D. Frank,et al.  Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[9]  F. Balestra,et al.  Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance , 1987, IEEE Electron Device Letters.

[10]  Yuan Taur,et al.  Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.