Greedy wire-sizing is linear time

The greedy wire-sizing algorithm (GWSA) has been experimentally shown to be very efficient, but no mathematical analysis on its convergence rate has ever been reported. In this paper, we consider GWSA for continuous wire sizing. We prove that GWSA converges linearly to the optimal solution, which implies that the run time of GWSA is linear with respect to the number of wire segments for any fixed precision of the solution. Moreover, we also prove that this is true for any starting solution. This is a surprising result because previously it was believed that in order to guarantee convergence, GWSA had to start from a solution in which every wire segment is set to the minimum (or maximum) possible width. Our result implies that GWSA can use a good starting solution to achieve faster convergence. We demonstrate this point by showing that the minimization of maximum delay and the minimization of area subject to maximum delay bound using Lagrangian relaxation can be sped up by more than 50%.

[1]  J. Cong,et al.  Interconnect design for deep submicron ICs , 1997, ICCAD 1997.

[2]  Jason Cong,et al.  An efficient approach to simultaneous transistor and interconnect sizing , 1996, ICCAD 1996.

[3]  Ren-Song Tsay,et al.  An exact zero-skew clock routing algorithm , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Jason Cong,et al.  Performance optimization of VLSI interconnect layout , 1996, Integr..

[5]  Hai Zhou,et al.  Optimal non-uniform wire-sizing under the Elmore delay model , 1996, ICCAD 1996.

[6]  Masato Edahiro,et al.  A Clustering-Based Optimization Algorithm in Zero-Skew Routings , 1993, 30th ACM/IEEE Design Automation Conference.

[7]  Chung-Ping Chen,et al.  A fast algorithm for optimal wire-sizing under Elmore delay model , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[8]  Martin D. F. Wong,et al.  Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[9]  W. C. Elmore The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[10]  Jason Cong,et al.  Simultaneous driver and wire sizing for performance and power optimization , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[11]  Yao-Wen Chang,et al.  Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation , 1996, 33rd Design Automation Conference Proceedings, 1996.

[12]  Jason Cong,et al.  Simultaneous buffer and wire sizing for performance and power optimization , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[13]  J. Cong,et al.  Optimal wiresizing under the distributed Elmore delay model , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[14]  Jason Cong,et al.  Optimal wiresizing for interconnects with multiple sources , 1995, TODE.