Design and verification of Dadda algorithm based Binary Floating Point Multiplier

This paper presents a fast single precision floating point multiplier. In most of the industrial areas like DSP, image processing, microprocessor, it is needed to do arithmetic operations very fast with greater accuracy and multiplier is widely used in these application areas. So we decide to increase the speed of floating point multiplication unit. To improve the speed of multiplier we minimize the delays in arithmetic operations at every stage. This is done by using Dadda algorithm for mantissa multiplication and Kogge-Stone adder for addition. These two algorithms need more number of LUT-flip flop pairs but speed is increases. The shifting technique is used to form partial product matrix which is new concept in Dadda algorithm, results in the optimization of design area. All basic modules of this multiplier are written in Verilog hardware descriptive language and targeted to two families of FPGA, Virtex6 and Virtex5 in Xilinx 13.1 ISE software. Design is simulated by using Model Sim6.3f. Synthesis results of both FPGA are compares with previously designed multiplier unit. Our design achieves maximum frequency of 851 MHz with 433 slices area and 1230 LUT-flip flop pairs in Virtex6 family.

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