A New Approach for Computing Multi-dimensional Dfts on Parallel Machines and Its Implementation on the Ipsc/860 Hypercube Sp-edics 4.1.5 Multidimensional Signal Processing: System Architectures and Implementations 2.2.7 Fast Algorithms: Algorithm Implementation in Hardware and Software

In this paper we propose a new approach for computing multi-dimensional DFTs that reduces interpro-cessor communications and is therefore suitable for eecient implementation on a variety of multiprocessor platforms including MIMD supercomputers and Clusters of Workstations. Group theoretic concepts are used to formulate a exible computational strategy that hybrids the Reduced Transform Algorithm (RTA) with the Good-Thomas factorization and can deal eeciently with non-power-of-2 sizes without resorting to zero-padding. The RTA algorithm is employed not as a data processing but rather as a book-keeping tool in order to decompose the problem into many smaller size sub-problems (lines) that can be solved independently by the processors. Implementation issues on an Intel iPSC/i860 hypercube are discussed and timing results for large 2D and 3D DFTs with index sets in Z=MP Z=KP and Z=N Z=MP Z=KP respectively are provided , where N; M; K are powers-of-two and P is a small prime number such as 3; 5; 7. The non-optimized realizations of the new Hybrid RTA approach are shown to outperform by as much as 70% the optimized assembly coded realizations of the traditional Row-Column method on the iPSC/860.