Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP

In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.

[1]  Kuo-Shu Kao,et al.  Achievement of low temperature chip stacking by a wafer-applied underfill material , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[2]  M. Brillhart,et al.  Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[3]  K. Saban.  Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity , Bandwidth , and Power Efficiency , 2009 .

[4]  John H. Lau,et al.  Effects of etch rate on scallop of through-silicon vias (TSVs) in 200mm and 300mm wafers , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[5]  Tai-Hong Chen,et al.  Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[6]  Suresh Ramalingam,et al.  Ceramics vs. low-CTE organic packaging of TSV silicon interposers , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[7]  Dongwook Kim,et al.  Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV) , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[8]  P. Tzeng,et al.  Electrical testing of blind Through-Silicon Via (TSV) for 3D IC integration , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[9]  John H. Lau,et al.  An Electrical Testing Method for Blind Through Silicon Vias (TSVs) for 3D IC Integration , 2011 .

[10]  J. H. Huang,et al.  Process integration and reliability test for 3D chip stacking with thin wafer handling technology , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[11]  Kuo-Shu Kao,et al.  Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[12]  Sheng-Tsai Wu,et al.  Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW) , 2011 .

[13]  John H. Lau,et al.  Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration , 2011 .

[14]  J. H. Lau,et al.  Thin Wafer Handling of 300mm Wafer for 3D IC Integration , 2011 .

[15]  J. H. Lau,et al.  How to select adhesive materials for temporary bonding and de-bonding of 200mm and 300mm thin-wafer handling for 3D IC integration? , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[16]  John H. Lau,et al.  A thermal performance measurement method for blind through silicon vias (TSVs) in a 300mm wafer , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[17]  B. Banijamali,et al.  Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA , 2011, Electronic Components and Technology Conference.

[18]  P. Tzeng,et al.  Impact of slurry in Cu CMP (chemical mechanical polishing) on Cu topography of Through Silicon Vias (TSVs), re-distribution layers, and Cu exposure , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[19]  Heng-Chieh Chien,et al.  Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[20]  Sheng-Tsai Wu,et al.  Energy release rate investigation for through silicon vias (TSVs) in 3D IC integration , 2011, 2011 12th Intl. Conf. on Thermal, Mechanical & Multi-Physics Simulation and Experiments in Microelectronics and Microsystems.

[21]  Kuo-Shu Kao,et al.  Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[22]  J. H. Lau,et al.  Wafer Bumping and Characterizations of Fine-Pitch Lead-Free Solder Microbumps on 12" (300mm) wafer for 3D IC Integration , 2011 .

[23]  Ren-Shin Cheng,et al.  Failure mechanism of 20 μm pitch microjoint within a chip stacking architecture , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[24]  Sheng-Tsai Wu,et al.  Thermal Performance of 3D IC Integration with Through-Silicon Via (TSV) , 2011 .