Optimization of silicon bipolar transistors for high current gain at low temperatures
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[1] J. Plummer,et al. A low-temperature NMOS technology with Cesium-implanted load devices , 1987, IEEE Transactions on Electron Devices.
[2] Takashi Hotta,et al. CMOS/bipolar circuits for 60-MHz digital processing , 1986 .
[3] P. M. Solomon,et al. Bipolar transistor design for optimized power-delay logic circuits , 1979 .
[4] V. L. Rideout,et al. Very small MOSFET's for low-temperature operation , 1977, IEEE Transactions on Electron Devices.
[5] R. Keyes,et al. The role of low temperatures in the operation of logic circuitry , 1970 .
[6] R. M. Swanson,et al. VIB-4 temperature dependence of minority electron mobility and bandgap narrowing in p + Si , 1987 .
[7] R. M. Swanson,et al. Majority and minority carrier transport in polysilicon emitter contacts , 1986, 1986 International Electron Devices Meeting.
[8] W. Dumke. The effect of base doping on the performance of Si bipolar transistors at low temperatures , 1981, IEEE Transactions on Electron Devices.
[9] R.D. Isaac,et al. Effect of emitter contact on current gain of silicon bipolar devices , 1980, IEEE Transactions on Electron Devices.
[10] H.P. Vyas,et al. Cryogenic behavior of scaled CMOS devices , 1984, 1984 International Electron Devices Meeting.
[11] G. Patton,et al. Physics, technology, and modeling of polysilicon emitter contacts for VLSI bipolar transistors , 1986, IEEE Transactions on Electron Devices.
[12] H. Bennett,et al. Improved concepts for predicting the electrical behavior of bipolar structures in silicon , 1983, IEEE Transactions on Electron Devices.
[13] A. Kamgar,et al. Miniaturization of Si MOSFET's at 77 K , 1982, IEEE Transactions on Electron Devices.
[14] T. Ikeda,et al. Advanced BiCMOS technology for high speed VLSI , 1986, 1986 International Electron Devices Meeting.
[15] W. Dumke. Effect of minority carrier trapping on the low-temperature characteristics of Si transistors , 1970 .
[16] J. Woo,et al. Non-ideal base current in bipolar transistors at low temperatures , 1987, IEEE Transactions on Electron Devices.
[17] Richard C. Jaeger,et al. Behavior of electrically small depletion mode MOSFETs at low temperature , 1981 .
[18] R.W. Dutton,et al. VLSI Process modeling—SUPREM III , 1983, IEEE Transactions on Electron Devices.
[19] Yuan Taur,et al. Submicrometer-channel CMOS for low-temperature operation , 1987, IEEE Transactions on Electron Devices.
[20] R.C. Jaeger,et al. Temperature dependence of latchup in CMOS circuits , 1984, IEEE Electron Device Letters.
[21] S. Hanamura,et al. Operation of Bulk CMOS Devices at Very Low Temperatures , 1983, 1983 Symposium on VLSI Technology. Digest of Technical Papers.
[22] Krishna C. Saraswat,et al. Effect of scaling of interconnections on the time delay of VLSI circuits , 1982 .
[23] J.D. Plummer,et al. Substrate current at cryogenic temperatures: Measurements and a two-dimensional model for CMOS technology , 1987, IEEE Transactions on Electron Devices.
[24] S. Tewksbury,et al. N-channel enhancement-mode MOSFET characteristics from 10 to 300 K , 1981, IEEE Transactions on Electron Devices.
[25] Hans-Martin Rein,et al. A contribution to the current gain temperature dependence of bipolar transistors , 1978 .
[26] J. Dziewior,et al. Auger coefficients for highly doped and highly excited silicon , 1977 .
[27] D. Tang. Heavy doping effects in p-n-p bipolar transistors , 1980, IEEE Transactions on Electron Devices.