A General Method for Compiling Event-Driven Simulations

We present a new approach to event-driven simulation that does not use a centralized run-time event queue, yet is capable of handling arbitrary models, including those with unclocked feedback and nonunit delay. The elimination of the event queue significantly reduces run-time overhead, resulting in faster simulation. We have implemented our algorithm in a prototype Verilog simulator called VeriSUIF. Using this simulator we demonstrate improved performance vs. a commercial simulator on a small set of programs.

[1]  Ernst G. Ulrich,et al.  Speed and Accuracy in Digital Network Simulation Based on Structural Modeling , 1982, 19th Design Automation Conference.

[2]  Barry K. Rosen,et al.  HSS--A High-Speed Simulator , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Craig Hansen,et al.  Hardware logic simulation by compilation , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[4]  LECSIM: a levelized event-driven compiled logic simulator , 1990, 27th ACM/IEEE Design Automation Conference.

[5]  David M. Lewis A hierarchical compiled code event-driven logic simulator , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  Zhicheng Wang,et al.  LECSIM: a levelized event driven compiled logic simulation , 1991, DAC '90.

[7]  Karem A. Sakallah,et al.  Ravel: assigned-delay compiled-code logic simulation , 1992, ICCAD.

[8]  Steven W. K. Tjiang,et al.  SUIF: an infrastructure for research on parallelizing and optimizing compilers , 1994, SIGP.

[9]  S. L. Coumeri,et al.  Benchmark descriptions for comparing the performance of Verilog and VHDL simulators , 1994, International Verilog HDL Conference.