Area-optimal sensing circuit designs in deep submicrometer STT-RAM

As the technology node scales down, a sufficient read current that is capable of achieving a target read yield cannot be used because of the read disturbance problem in spin-transfer-torque random access memory (STT-RAM). As an alternative method, increasing the sensing circuit (SC) area is generally considered because it can reduce the threshold voltage (Vth) variations. However, the increased SC area can adversely reduce the read yield due to the increased load capacitance. The effects of the increased area on read yield can be different according to the SCs because of their own characteristics. In this work, the trends of read yield according to the area are analyzed for two representative SCs, and the areas of two SCs are optimally designed to have high read yield.

[1]  Seong-Ook Jung,et al.  A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory , 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

[2]  Luan Tran,et al.  45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[3]  Seong-Ook Jung,et al.  A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM) , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[4]  S. Watts,et al.  Latest Advances and Roadmap for In-Plane and Perpendicular STT-RAM , 2011, 2011 3rd IEEE International Memory Workshop (IMW).

[5]  H. Hoenigschmid,et al.  A high-speed 128-kb MRAM core for future universal memory applications , 2004, IEEE Journal of Solid-State Circuits.

[6]  J. Slaughter,et al.  A Fully Functional 64 Mb DDR3 ST-MRAM Built on 90 nm CMOS Technology , 2013, IEEE Transactions on Magnetics.

[7]  M. Hosomi,et al.  A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..