Parity bit code: achieving a complete fault coverage in the design of TSC combinational networks
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[1] Prithviraj Banerjee,et al. RSYN: a system for automated synthesis of reliable multilevel circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[2] Kurt Keutzer. DAGON: Technology Binding and Local Optimization by DAG Matching , 1987, DAC.
[3] M. Fujita,et al. Boolean technology mapping for both ECI and CMOS circuits based on permissible functions and binary decision diagrams , 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[4] Shin-ichi Minato. Multi-Level Logic Synthesis Using ZBDDs , 1996 .
[5] Gernot Metze,et al. Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes , 1973, IEEE Transactions on Computers.
[6] Nur A. Touba,et al. Logic Synthesis Techniques For Reduced Area Implementation Of Multilevel Circuits With Concurrent Error Detection , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[7] Robert K. Brayton,et al. Multilevel logic synthesis , 1990, Proc. IEEE.
[8] Eiji Fujiwara,et al. Probability to Achieve TSC Goal , 1996, IEEE Trans. Computers.