Evolutionary Algorithms in Computer-Aided Design of Integrated Circuits

An increasing number of successful applications of Evolutionary Algorithms (EAs) within Computer Aided Design (CAD) of Integrated Circuits (ICs) is reported in the literature. The problems dealt with in this eld consist of sequences of sub-problems, which are characterized by being NP-hard, large and mutually dependent. This very high level of complexity should make the EA a well suited approach, at least in principle. However, the EA is of practical interest to the CAD community if and only if it is competitive to the existing approaches with respect to performance. With this fact as the starting point, the purpose of this paper is to discuss how to develop high-performance EAs for CAD of ICs. After reviewing a number of recent, performance competitive EAs for key problems in CAD of ICs, the common characteristics of these algorithms are discussed. They all exploit problem speciic knowledge in various ways or are integrated with other heuris-tics. The paper also discusses performance evaluation principles. To make an impact, it is crucial that performance is evaluated using the measures commonly applied in the CAD eld. The practical implications hereof for EA-based applications are addressed. Finally, we discuss a model for EAs to learn heuris-tics starting from a given set of basic operations. The diierence to other previous applications of EAs in CAD of ICs is that the EA does not solve the problem directly. Rather, it developes strategies for solving the problem.

[1]  Ernest S. Kuh,et al.  EXPLORER: an interactive floorplanner for design space exploration , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[2]  Rolf Drechsler,et al.  A multi-layer detailed routing approach based on evolutionary algorithms , 1997, Proceedings of 1997 IEEE International Conference on Evolutionary Computation (ICEC '97).

[3]  Irith Pomeranz,et al.  On improving genetic optimization based test generation , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[4]  Rolf Drechsler,et al.  OFDD based minimization of fixed polarity Reed-Muller expressions using hybrid genetic algorithms , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[5]  Pinaki Mazumder,et al.  SAGA : a unification of the genetic algorithm with simulated annealing and its application to macro-cell placement , 1994, Proceedings of 7th International Conference on VLSI Design.

[6]  Kenji Kani Computer Aided Design of Integrated Circuits , 1971 .

[7]  Paolo Prinetto,et al.  Partial scan flip flop selection for simulation-based sequential ATPGs , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[8]  Jens Lienig,et al.  A parallel genetic algorithm for two detailed routing problems , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[9]  Lawrence. Davis,et al.  Handbook Of Genetic Algorithms , 1990 .

[10]  Elizabeth M. Rudnick,et al.  A genetic approach to test application time reduction for full scan and partial scan circuits , 1995, Proceedings of the 8th International Conference on VLSI Design.

[11]  Rolf Drechsler,et al.  A hybrid genetic algorithm for the channel routing problem , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[12]  H. Esbensen A macro-cell global router based on two genetic algorithms , 1994, EURO-DAC '94.

[13]  Rolf Drechsler,et al.  A Genetic Algorithm for Minimization of Fixed Polarity Reed-Muller Expressions , 1995, ICANNGA.

[14]  Bernd Becker,et al.  On optimizing BIST-architecture by using OBDD-based approaches and genetic algorithms , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[15]  Paolo Prinetto,et al.  Comparing topological, symbolic and GA-based ATPGs: an experimental approach , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[16]  Jens Lienig,et al.  A Parallel Genetic Algorithm for , 1997 .

[17]  Rolf Drechsler,et al.  Minimization of OKFDDs by Genetic Algorithms , 1996 .

[18]  Andreas Kuehlmann,et al.  Grammar-based optimization of synthesis scenarios , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[19]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[20]  R. Drechsler,et al.  Learning heuristics by genetic algorithms , 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

[21]  Henrik Esbensen,et al.  A genetic algorithm for the Steiner Problem in a graph , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[22]  Jens Lienig,et al.  A new genetic algorithm for the channel routing problem , 1994, Proceedings of 7th International Conference on VLSI Design.

[23]  Rolf Drechsler,et al.  Learning Heuristics for OBDD Minimization by Evolutionary Algorithms , 1996, PPSN.

[24]  R. Drechsler,et al.  A genetic algorithm for the construction of small and highly testable OKFDD-circuits , 1996 .

[25]  Rolf Drechsler,et al.  Learning heuristics for OKFDD minimization by evolutionary algorithms , 1996, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

[26]  Irith Pomeranz,et al.  GAFPGA: Genetic algorithm for FPGA technology mapping , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

[27]  Rolf Drechsler,et al.  A genetic algorithm for variable ordering of obdds , 1996 .

[28]  Zbigniew Michalewicz,et al.  Heuristic methods for evolutionary computation techniques , 1996, J. Heuristics.

[29]  Prathima Agrawal,et al.  CONTEST: a concurrent test generator for sequential circuits , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[30]  Paolo Prinetto,et al.  GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  Byung Ro Moon,et al.  A Fast and Stable Hybrid Genetic Algorithm for the Ratio-Cut Partitioning Problem on Hypergraphs , 1994, 31st Design Automation Conference.

[32]  Tsutomu Sasao,et al.  Logic Synthesis and Optimization , 1997 .

[33]  Daniel G. Saab,et al.  Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0 , 1994, ICCAD.

[34]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[35]  Michael S. Hsiao,et al.  Alternating strategies for sequential circuit ATPG , 1996, Proceedings ED&TC European Design and Test Conference.

[36]  Rolf Drechsler,et al.  A genetic algorithm for RKRO minimization , 1997 .

[37]  Rolf Drechsler,et al.  Influencing parameters of evolutionary algorithms for sequencing problems , 1997, Proceedings of 1997 IEEE International Conference on Evolutionary Computation (ICEC '97).

[38]  Rolf Drechsler,et al.  Minimization of BDDs by Evolutionary Algorithms , 1997 .

[39]  David E. Goldberg,et al.  Genetic Algorithms in Search Optimization and Machine Learning , 1988 .

[40]  Elizabeth M. Rudnick,et al.  Sequential Circuit Test Generation in a Genetic Algorithm Framework , 1994, 31st Design Automation Conference.

[41]  Paolo Prinetto,et al.  Advanced techniques for GA-based sequential ATPGs , 1996, Proceedings ED&TC European Design and Test Conference.