A Configware Approach for the Implementation of a LVQ Neural Network

This paper describes a methodology for the imple- mentation of a Learning Vector Quantization (LVQ) neural net- work in a Field Programmable Gate Array (FPGA) device, es- pecially suited for applications requiring fast throughoutput. A special feature of the implementation is a combinatorial mod- ule for distance comparison that allows the execution of this im- portant operation for a LVQ in just one clock cycle. The con- trol code of the LVQ is described by a finite state machine and parametrically programmed in VHDL. The final neural net- work was implemented with 64 dimensions, 16 subclusters and 2 classes, using an ACEX1k100 reconfigurable device. Using this system with a clock rate of 25MHz, a full classification can be done in 334"s, thus enabling real-time performance for many real-world applications. Keywords: LVQ, FPGA, Hardware.