A 3D flash ADC structure for high-speed communication applications

A 5-bit highly-accurate, low-power, and high-performance three-dimensional (3D) flash analog to digital converter (ADC) is presented for communication system applications. This architecture implements very short vertical interconnections, namely through-silicon via (TSV) channels to improve dynamic performance, increase power efficiency, and decrease the silicon area. To validate the proposed 3D flash ADC design, the architecture is simulated in a 65 nm CMOS technology. The 3D TSV channels (i.e., TSV and μbumps) are modeled to generate S-parameters using a 3D EM solver tool (i.e., HFSS). The demonstrated results reveal that the whole structure achieves SFDR of 39.8 and power consumption of 5.4 at 400 MS/s sampling rate.