Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology

In this paper, a multi-level wordline driver scheme is presented to improve SRAM read and write stability while lowering power consumption during hold operation. The proposed circuit applies a shaped wordline voltage pulse during read mode and a boosted wordline pulse during write mode. During read, the applied shaped pulse is tuned at nominal voltage for short period of time, whereas for the remaining access time, the wordline voltage is reduced to a lower level. This pulse results in improved read noise margin without any degradation in access time which is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during hold mode, the wordline voltage starts from a negative value and reaches zero voltage, resulting in a lower leakage current compared to conventional SRAM. Our simulations using TSMC 65nm process show that the proposed wordline driver results in 2X improvement in static read noise margin while the write margin is improved by 3X. In addition, the total leakage of the proposed SRAM is reduced by 10% while the total power is improved by 12% in the worst case scenario of a single SRAM cell. The total area penalty is 10% for a 128Kb standard SRAM array.

[1]  Ching-Te Chuang,et al.  SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Cameron McNairy,et al.  Itanium 2 Processor Microarchitecture , 2003, IEEE Micro.

[3]  Kaushik Roy,et al.  Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  M. Yabuuchi,et al.  A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist , 2009, 2009 Symposium on VLSI Circuits.

[5]  M. Sharifkhani,et al.  SRAM Cell Stability: A Dynamic Perspective , 2009, IEEE Journal of Solid-State Circuits.

[6]  Kevin Zhang,et al.  A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation , 2011, IEEE Journal of Solid-State Circuits.

[7]  K Roy,et al.  A Physics-Based Three-Dimensional Analytical Model for RDF-Induced Threshold Voltage Variations , 2011, IEEE Transactions on Electron Devices.

[8]  Naveen Verma,et al.  A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[9]  T. Iwasaki,et al.  A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment , 2008, 2008 IEEE Symposium on VLSI Circuits.

[10]  B. M. Gordon,et al.  Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.

[11]  Yehea I. Ismail,et al.  Accurate Estimation of SRAM Dynamic Stability , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Koji Nii,et al.  A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[13]  Peter W. Cook,et al.  A 15-ns CMOS 64K RAM , 1986 .

[14]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[15]  Duane S. Boning,et al.  Using a statistical metrology framework to identify systematic and random sources of die- and wafer-level ILD thickness variation in CMP processes , 1995, Proceedings of International Electron Devices Meeting.

[16]  Atsushi Kawasumi,et al.  A process-variation-tolerant dual-power-supply SRAM with 0.179µm2 Cell in 40nm CMOS using level-programmable wordline driver , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.