Cubic Packing with Various Candidates for 3D IC Design

In this paper, we introduce various candidates for circuit blocks so that the floorplanner can dynamically choose the implementations of blocks to optimize the whole chip. Especially in 3D IC design, some components may occupy more than one layer, we propose a novel method to optimize the cubic packing with various candidates. Based on 3D-CBL (3-dimensional corner block list) representation, we can handle the layer number constraints heuristically and we guarantee the feasibility of the final results. Experimental results show that our algorithm is effective and efficient

[1]  Erich Barke,et al.  An upper bound for 3D slicing floorplans , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[2]  Yici Cai,et al.  Corner block list: an effective and efficient topological representation of non-slicing floorplan , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[3]  Yoshiko Wakabayashi,et al.  An algorithm for the three-dimensional packing problem with asymptotic performance analysis , 1997, Algorithmica.

[4]  Kam-Hoi Cheng,et al.  On Three-Dimensional Packing , 1990, SIAM J. Comput..

[5]  Sheqin Dong,et al.  3D CBL: An Efficient Algorithm for General 3-Dimensional Packing Problems * , 2005 .

[6]  Jürgen Teich,et al.  Optimization of Dynamic Hardware Reconfigurations , 2004, The Journal of Supercomputing.

[7]  Kam-Hoi Cheng,et al.  Heuristic Algorithms for On-Line Packing in Three Dimensions , 1992, J. Algorithms.

[8]  Sheqin Dong,et al.  3D CBL: an efficient algorithm for general 3D packing problems , 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

[9]  Jürgen Teich,et al.  Optimal FPGA module placement with temporal precedence constraints , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[10]  Yoji Kajitani,et al.  The 3 D-Packing by Meta Data Structure and Packing Heuristics , 2000 .

[11]  Yao-Wen Chang,et al.  Temporal floorplanning using 3D-subTCG , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).