Scheduling and resource binding for low power

Abstract: Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during the scheduling and resource-binding steps of high-level synthesis. Algorithms for these steps targeting at low-power data-paths and trading off, in some cases, speed and area for low power are presented. The algorithms focus on reducing the activity of the functional units (adders, multipliers) by minimizing the transitions of their input operands. The power consumption of the functional units accounts for a large fraction of the overall data-path power budget.

[1]  Farid N. Najm,et al.  Towards a high-level power estimation capability , 1995, ISLPED '95.

[2]  N. Ahmed,et al.  Discrete Cosine Transform , 1996 .

[3]  Thomas D. Burd,et al.  Energy efficient CMOS microprocessor design , 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.

[4]  Niraj K. Jha,et al.  Behavioral synthesis for low power , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[5]  Jan M. Rabaey,et al.  Activity-sensitive architectural power analysis for the control path , 1995, ISLPED '95.

[6]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[7]  Barry J. Shepherd,et al.  Graphics file formats - reference and guide , 1994 .

[8]  William H. Press,et al.  The Art of Scientific Computing Second Edition , 1998 .

[9]  Abhijit Chatterjee,et al.  Synthesis of low power linear DSP circuits using activity metrics , 1994, Proceedings of 7th International Conference on VLSI Design.

[10]  Radu Marculescu,et al.  Information theoretic measures of energy consumption at register transfer level , 1995, ISLPED '95.

[11]  F. A. Seiler,et al.  Numerical Recipes in C: The Art of Scientific Computing , 1989 .

[12]  C. Johnson,et al.  Theory and design of adaptive filters , 1987 .

[13]  Hugo De Man,et al.  Global Communication and Memory Optimizing Transformations for Low Power Systems , 1994 .

[14]  Miodrag Potkonjak,et al.  HYPER-LP: a system for power minimization using architectural transformations , 1992, ICCAD.

[15]  Jordi Cortadella,et al.  High-level synthesis techniques for reducing the activity of functional units , 1995, ISLPED '95.

[16]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[17]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[18]  Ramesh Karri,et al.  Simultaneous scheduling and binding for power minimization during microarchitecture synthesis , 1995, ISLPED '95.

[19]  William H. Press,et al.  Book-Review - Numerical Recipes in Pascal - the Art of Scientific Computing , 1989 .

[20]  Sun-Yuan Kung,et al.  On supercomputing with systolic/wavefront array processors , 1984 .

[21]  Israel Koren.  Computer arithmetic algorithms , 1993 .