论文信息 - The CMOS analog multiplier free from mobility reduction

The CMOS analog multiplier free from mobility reduction

In this paper, a CMOS analog multiplier circuit is proposed. It consists of eight voltage subtractors, four voltage sources and a multiplier cell. Its major advantage is its freedom from mobility reduction, so it has low total harmonic distortion (THD). For the proposed multiplier cell, its inputs are applied to the drains of the input cell transistors through the voltage sources. Their gates are fixed to the same bias voltage to remove the effect of mobility reduction. The simulation results show that the THD is less than 0.13% for 0.8 V/sub P-P/ input signal at 2.5 V supply voltage, and that the -3 dB bandwidth is up to 38 MHz.

K. Dejhan | N. Suwanchatree | P.P.I. Chaisayun

[1] Akira Hyogo,et al. Design of very low‐distortion, four‐quadrant analog multiplier‐type CMOS‐OTA considering variation of mobility according to the gate voltage , 1994 .

[2] Mohammed Ismail,et al. Four-quadrant CMOS/BiCMOS multipliers using linear-region MOS transistors , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

[3] Shen-Iuan Liu,et al. CMOS four-quadrant multiplier using bias feedback techniques , 1994 .

[4] K. Bult,et al. A CMOS Four-Quadrant Analog Multiplier , 1986 .

[5] J.S. Pena-Finol,et al. A MOS four-quadrant analog multiplier using the quarter-square technique , 1987 .

[6] E. Seevinck,et al. A versatile CMOS linear transconductor/square-law function , 1987 .

[7] S. B. Park,et al. Design and implementation of a new four-quadrant MOS analog multiplier , 1992 .

[8] Z. Wang,et al. A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance , 1991 .

[9] Ho-Jun Song,et al. An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers , 1990 .

[10] Stephen Wong,et al. Impact of Scaling on MOS Analog Performance , 1983 .

[11] Cheng-Chieh Chang,et al. CMOS analog divider and four-quadrant multiplier using pool circuits , 1995 .

[12] Eitake Ibaragi,et al. A CMOS Analog Multiplier Free from Mobility Reduction and Body Effect , 1999 .