Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs

In this paper, we propose the sub-block Active-Mode Power Gating (AMPG) scheme to reduce the active-mode leakage and apply it to the 32-bit Carry Select Adder (CSA), where the sub-blocks are activated and deactivated according to the idleness during the active time. By doing so, we can reduce the active-mode energy by 21% at the cycle time of 10 ns for the 22-nm node compared to the conventional AMPG. The critical path delay is degraded as little as 1% in the sub-block AMPG. For a given power budget as small as 100μW, the new sub-block AMPG with 32-nm node can run faster by 47% than the conventional AMPG.

[1]  Pradip Bose,et al.  Microarchitectural techniques for power gating of execution units , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[2]  Julien Penders,et al.  Energy Harvesting for Autonomous Wireless Sensor Networks , 2010, IEEE Solid-State Circuits Magazine.

[3]  David Flynn,et al.  Sub-clock power-gating technique for minimising leakage power during active mode , 2011, 2011 Design, Automation & Test in Europe.

[4]  Kimiyoshi Usami,et al.  A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals , 2006, 2006 International Conference on Computer Design.

[5]  Youngsoo Shin,et al.  Synthesis and implementation of active mode power gating circuits , 2010, Design Automation Conference.

[6]  Hiroshi Kawaguchi,et al.  Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.