A reduced-field design concept for high-performance bipolar transistors

A device profile design concept that reduces the junction field, and thus the high-field induced leakage currents as well as the avalanche current, is described. The insertion of an i-layer of thickness equal to the depletion-layer width of the original n/sup +/-p/sup +/ junction can lower the junction field by about a factor of two. Computer studies show that using this design, the collector avalanche current can be reduced by more than one order, while compromising little in the switching speed of the transistor.<<ETX>>

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