Systematic defects in deep sub-micron technologies

Defects due to process-design interaction have a systematic nature. Therefore they can have a profound impact on yield. The capability to detect (and correct) them is a requirement to continue to follow Moore's law. Most of the systematic defects are detected during the process development. These defects are detectable with test structures or visual inspection tools. However some process marginalities are only show-up in the topology of 'real' designs. Moreover, these defects are often not detectable with stuck-at testing. We show two examples of process related defects which could only be detected with more advanced test methods such as transition fault testing and low voltage testing. To correct systematic problems, however, one should not only have the capability to detect defects but also to identify them. Our examples show that other tests could have been far more sensitive in detecting systematic issues. Therefore the detection of systematic defects gives new requirements to test suites and can only be achieved with a shift in the position of manufacturing test.

[1]  Camelia Hora,et al.  An effective diagnosis method to support yield improvement , 2002, Proceedings. International Test Conference.

[2]  Bram Kruseman,et al.  Comparison of I/sub DDQ/ testing and very-low voltage testing , 2002, Proceedings. International Test Conference.

[3]  Víctor H. Champac,et al.  Resistive opens in a class of CMOS latches: analysis and DFT , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[4]  Keith Baker,et al.  Shmoo Plotting: The Black Art of IC Testing , 1997, IEEE Des. Test Comput..

[5]  Edward J. McCluskey,et al.  Very-low-voltage testing for weak CMOS logic ICs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[6]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[7]  Edward J. Nowak,et al.  Maintaining the benefits of CMOS scaling when scaling bogs down , 2002, IBM J. Res. Dev..

[8]  John Paul Shen,et al.  Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.

[9]  A. Ferris-Prabhu.  Role of defect size distribution in yield modeling , 1985, IEEE Transactions on Electron Devices.

[10]  Heinrich Theodor Vierhaus,et al.  CMOS bridges and resistive transistor faults: IDDQ versus delay effects , 1993, Proceedings of IEEE International Test Conference - (ITC).

[11]  Phil Nigh.  What defects escape our tests ... and how will we detect them in the future , 2000 .

[12]  Pia Sanda,et al.  The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA) , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).