TH-1: China’s first petaflop supercomputer
暂无分享,去创建一个
Kai Lu | Xuejun Yang | Qingfeng Hu | Canqun Yang | Xiangke Liao | Jinshu Su | Liquan Xiao | Weixia Xu | Junqiang Song | Qiang Dou | Juping Jiang | Xuejun Yang | Jinshu Su | Xiangke Liao | Kai Lu | Q. Dou | Canqun Yang | Weixia Xu | Liquan Xiao | Junqiang Song | Qingfeng Hu | Juping Jiang
[1] David Kirk,et al. NVIDIA cuda software and gpu parallel computing architecture , 2007, ISMM '07.
[2] Sung-Eun Choi,et al. Compiler-generated staggered checkpointing , 2004 .
[3] Edward J. McCluskey,et al. Error detection by duplicated instructions in super-scalar processors , 2002, IEEE Trans. Reliab..
[4] Huiyang Zhou,et al. Understanding software approaches for GPGPU reliability , 2009, GPGPU-2.
[5] Ying Zhang,et al. A 64-bit stream processor architecture for scientific applications , 2007, ISCA '07.
[6] Hyesoon Kim,et al. Qilin: Exploiting parallelism on heterogeneous multiprocessors with adaptive mapping , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[7] Scott Pakin,et al. Entering the petaflop era: the architecture and performance of Roadrunner , 2008, HiPC 2008.
[8] Michael L. Scott,et al. Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling , 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.