Compression of VLSI test data by arithmetic coding

This work presents arithmetic coding and its application to data compression for VLSI testing. The use of arithmetic codes for compression results in a codeword whose length is close to the optimal value as predicted by entropy in information theory. Previous techniques (such as those based on Huffman or Golomb coding) result in optimal codes for test data sets in which the probability model of the symbols satisfies specific requirements. We show that Huffman and Golomb codes result in large differences between entropy bound and sustained compression. We present compression results of arithmetic coding for circuits through a practical integer implementation of arithmetic coding/decoding and analyze its deviation from the entropy bound as well. A software implementation approach is proposed and studied in detail using industrial embedded DSP cores.

[1]  Krishnendu Chakrabarty,et al.  System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Janak H. Patel,et al.  Test set compaction algorithms for combinational circuits , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[3]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[4]  Krishnendu Chakrabarty,et al.  Huffman encoding of test sets for sequential circuits , 1998, IEEE Trans. Instrum. Meas..

[5]  Khalid Sayood,et al.  Introduction to Data Compression , 1996 .

[6]  Saudi Arabia.  A GEOMETRIC-PRIMITIVES-BASED COMPRESSION SCHEME FOR TESTING SYSTEMS-ON-A-CHIP , 2005 .

[7]  Bashir M. Al-Hashimi,et al.  Variable-length input Huffman coding for system-on-a-chip test , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Yervant Zorian,et al.  Test requirements for embedded core-based systems and IEEE P1500 , 1997, Proceedings International Test Conference 1997.

[9]  Nur A. Touba,et al.  An efficient test vector compression scheme using selective Huffman coding , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Nur A. Touba,et al.  Using an embedded processor for efficient deterministic testing of systems-on-a-chip , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

[11]  Fabrizio Lombardi,et al.  ATE-amenable test data compression with no cyclic scan registers , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[12]  Nur A. Touba,et al.  Test vector decompression via cyclical scan chains and its application to testing core-based designs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[13]  Nur A. Touba,et al.  Matrix-based test vector decompression using an embedded processor , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[14]  Glen G. Langdon,et al.  An Introduction to Arithmetic Coding , 1984, IBM J. Res. Dev..