Systematic design and optimization of operational transconductance amplifier using gm/ID design methodology

Abstract The simple square-law MOSFET model fails to describe the behavior of short channel and moderate/weak inversion devices. The gm/ID methodology is a promising technique that addresses the square-law shortcomings and bridges the gap between hand analysis and simulation. This paper describes a systematic procedure for the design of a single-stage operational-transconductance amplifier (OTA) using the gm/ID methodology. Both small signal and large signal specifications are used to constrain the design process, which is graphically illustrated using trade-off charts. The presented design procedure is automated using MATLAB, and an iterative procedure is used to take the OTA self-loading into consideration. Moreover, an automated optimization procedure is presented to maximize the speed of a unity-gain buffer under current consumption, DC gain, and input capacitance constraints. The designed circuits are verified using Cadence Spectre and the 180 nm Predictive Technology Model (PTM), where the simulation results are in close agreement with hand analysis and automation results.

[1]  David Blaauw,et al.  Dual-slope capacitance to digital converter integrated in an implantable pressure sensing system , 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).

[2]  Denis Flandre,et al.  Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology , 1997 .

[3]  Takayuki Konishi,et al.  Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology , 2011, IEICE Trans. Electron..

[4]  Paul Jespers.  The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches , 2009 .

[5]  Denis Flandre,et al.  A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA , 1996, IEEE J. Solid State Circuits.

[6]  B. J. Maundy,et al.  Synthesis and analysis of fully differential filters using two port networks , 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

[7]  Khaled N. Salama,et al.  A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  HyungWon Kim,et al.  Ultra-low power OTA based on bias recycling and subthreshold operation with phase margin enhancement , 2017, Microelectron. J..

[9]  David Blaauw,et al.  Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.

[10]  Siddharth Seth,et al.  Settling time and noise optimization of a three-stage operational transconductance amplifier , 2013, 2012 IEEE International Symposium on Circuits and Systems.

[11]  Ahmed S. Elwakil,et al.  Single Transistor Active Filters: What is Possible and What is Not , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Boris Murmann,et al.  Systematic Design of Analog CMOS Circuits: Using Pre-Computed Lookup Tables , 2017 .

[13]  Behzad Razavi,et al.  Design of Analog CMOS Integrated Circuits , 1999 .