A Modified ScanD Flip-flop Design to Reduce Test Power .
暂无分享,去创建一个
[1] S. Chakravarty,et al. Two techniques for minimizing power dissipation in scan circuits during test application , 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).
[2] Karsten P. Ulland,et al. Vii. References , 2022 .
[3] Zainalabedin Navabi,et al. Reducing test power, time and data volume in SoC testing using selective trigger scan architecture , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.
[4] Nur A. Touba,et al. Reducing power dissipation during test using scan chain disable , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.