A Modified ScanD Flip-flop Design to Reduce Test Power .

Power consumption in scan based testing is high due to the toggling of the combinational logic during the scan shift. In this paper, we present a modified Scan Flip-flop architecture with a minimal area overhead which completely eliminates the switching power dissipation and also reduces the leakage power in the combination circuit during the shift phase of a scan based test. This also enables us to increase the shift frequency since power is no longer a limiting factor during scan shift and help in achieving test time reduction. Index Scan based test. Scan Flip-flop, scan per vector.

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