On modeling parasitic control loops in RF SoCs: Cross-coupling and spurious analysis

Migrating solutions to the most advance CMOS process node addresses cost reduction but increases RF interference within a SoC. In this paper we address the issue of design verification of single-chip RF SOCs in the presence of unintentional cross-couplings and leakages due to proximity of aggressors and victims. We will extend a previously presented VHDL based simulation methodology that accepts RF input and analyzes receiver BER performance, transmitter output distortion and phase noise by processing several thousand packets of baseband information while compensation algorithms are simultaneously executed. This approach allows building complex RF SoC systems based on behavioral models and has been successfully applied to investigate system behavior in the presence of aggressing nodes that create parasitic control loops due to unintentional and undesirable coupling paths.