The VLSI implementation of a square root algorithm

VLSI implementation of a square root algorithm is studied. Two possible implementations of the basic non-restoring algorithm are presented — the second is more area-efficient and modular than the first. The implementations are simple and easy to control, but, at the same time, are more area-time efficient than many existing designs. A hardware algorithm suited to microprogram implementation is also given. Extension of the algorithms to achieve ½ bit precision is discussed.

[1]  Stanislaw Majerski,et al.  Square-root algorithms for high-speed digital circuits , 1983, 1983 IEEE 6th Symposium on Computer Arithmetic (ARITH).

[2]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[3]  J. S. Wholey.  IEEE Transactions on Electronic Computers , 1963 .

[4]  Gernot Metze,et al.  Minimal Square Rooting , 1965, IEEE Trans. Electron. Comput..

[5]  Ivan Flores,et al.  The logic of computer arithmetic , 1963 .