Simulation of the Parasitic Interconnect Capacitance in the DRAM with the Stacked Structures

With development of high density bit DRAM,the parasitic interconnect capacitance is becoming an important factor to affect the circuit performance such as time delay,power consumption and noise etc.While the multi level interconnection and complex storage capacitor cell are used in DRAM layout to increase the integrated density and improve performance of the integrated circuits,a powerful parasitic interconnect capacitance simulator is required urgently.A simulator based on the BEM,with high precision,high speed and strong ability to treat complicated structures,is presented in this paper.Some tested results of the parasitic interconnect capacitance are used to analyse the performance in DRAM circuits.