High speed Fp multipliers and adders on FPGA platform

The paper proposes high speed FPGA implementations of adders and multipliers in Fp. The work shows through experimental results that due to optimized addition chain available in such devices, Karatsuba decomposition upto a particular level improves the performance. Further the paper modifies existing interleaved multiplier using Montgomery ladder and the high speed adder circuits. Extensive experiments have been performed. The result shows that the proposed design provides 70% speedup from the best known designs.

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