Conflict analysis in multiprocess synthesis for optimized system integration
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[1] Rainer Laur,et al. Time constrained modulo scheduling with global resource sharing , 1999, DATE '99.
[2] John William Hagerman. Synthesis of multiple process digital systems , 1995 .
[3] Wolfgang Rosenstiel,et al. Synchronization detection for multi-process hierarchical synthesis , 1998, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210).
[4] Erik L. Dagless,et al. Synchronous parallel controller synthesis from behavioural multiple-process VHDL description , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.
[5] Wayne Hendrix Wolf,et al. High-Level Modeling and Synthesis of Communicating Processes Using VHDL (Special Issue on Synthesis and Verification of Hardware Design) , 1993 .
[6] Massoud Pedram,et al. Codex-dp: co-design of communicating systems using dynamicprogramming , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Wolfgang Rosenstiel,et al. Communication analysis for system-on-chip design , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[8] Donald E. Thomas,et al. Multiple-process behavioral synthesis for mixed hardware-software systems , 1995 .
[9] Wolfgang Rosenstiel,et al. Resource sharing in hierarchical synthesis , 1997, ICCAD 1997.
[10] Rainer Laur,et al. Resource constrained modulo scheduling with global resource sharing , 1998, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210).
[11] Wolfgang Rosenstiel,et al. Worst-case performance analysis of parallel, communicating software processes , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).
[12] Sujit Dey,et al. Resource budgeting for Multiprocess High-level synthesis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[13] Arun K. Majumdar,et al. Synchronization of communicating modules and processes in high level synthesis , 1995, Proceedings of the 8th International Conference on VLSI Design.
[14] Petru Eles,et al. Synthesis of systems specified as interacting VHDL processes , 1996, Integr..
[15] Giovanni De Micheli,et al. Analysis and synthesis of concurrent digital circuits using control-flow expressions , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[16] Pierre G. Paulin,et al. Force-directed scheduling for the behavioral synthesis of ASICs , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[17] William Pugh,et al. The Omega test: A fast and practical integer programming algorithm for dependence analysis , 1991, Proceedings of the 1991 ACM/IEEE Conference on Supercomputing (Supercomputing '91).