Tester-Assisted Calibration and Screening for Digitally-Calibrated ADCs

This paper presents a low-cost production test strategy for digitally-calibrated analog-to-digital converters (ADCs) that incorporate an equalization-based background calibration scheme. The test time of these designs is dominated by the long calibration time required prior to conducting the final testing. To reduce overall test time, we present a two-step calibration approach that significantly reduces calibration time without compromising test coverage. In addition, by analyzing the data obtained in calibration, devices that fail certain static or dynamic specifications can be identified without incurring any additional test time beyond calibration, thereby enabling early rejection. To minimize calibration time and maximize failing symptoms for fault detection, we propose using specific calibration stimuli. Simulation results for a pipelined ADC shows that the proposed strategy reduces the total test time by 80%. This is achieved by reducing the calibration time, as well as by prescreening a good fraction of defective devices that fail static and dynamic specifications including the gain/offset errors and the effective number of bits (ENOB).

[1]  Borivoje Nikolic,et al.  Least mean square adaptive digital background calibration of pipelined analog-to-digital converters , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Soon-Jyh Chang,et al.  A Reduced Code Linearity Test Method for Pipelined A/D Converters , 2008, 2008 17th Asian Test Symposium.

[3]  Hsiu-Ming Chang,et al.  TAC: Testing time reduction for digitally-calibrated designs , 2009, 2009 IEEE 15th International Mixed-Signals, Sensors, and Systems Test Workshop.

[4]  Shalabh Goyal,et al.  Alternate Test Methodology for High Speed A/D Converter Testing on Low Cost Tester , 2005, 14th Asian Test Symposium (ATS'05).

[5]  Boris Murmann.  Digitally Assisted Analog Circuits , 2006, IEEE Micro.

[6]  S. Haykin,et al.  Adaptive Filter Theory , 1986 .

[7]  Bin-Da Liu,et al.  Histogram Based Testing Strategy for ADC , 2006, 2006 15th Asian Test Symposium.

[8]  M. F. Wagdy,et al.  Determining ADC effective number of bits via histogram testing , 1991 .

[9]  Kwang-Ting Cheng,et al.  Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study , 2010, J. Electron. Test..

[10]  Abhijit Chatterjee,et al.  Test time reduction of successive approximation register A/D converter by selective code measurement , 2005, IEEE International Conference on Test, 2005..

[11]  Simon Haykin,et al.  Adaptive Filter Theory 4th Edition , 2002 .

[12]  Kwang-Ting Cheng,et al.  Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCs , 2008, 2008 17th Asian Test Symposium.

[13]  Kwang-Ting Cheng,et al.  Calibration and Testing Time Reduction Techniques for a Digitally-Calibrated Pipelined ADC , 2009, 2009 27th IEEE VLSI Test Symposium.

[14]  P.J. Hurst,et al.  A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration , 2004, IEEE Journal of Solid-State Circuits.

[15]  J. Blair.  Histogram measurement of ADC nonlinearities using sine waves , 1994 .

[16]  Gin-Kou Ma,et al.  A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[17]  Yun Chiu.  Recent advances in digital-domain background calibration techniques for multistep analog-to-digital converters , 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

[18]  Seung-Chul Lee,et al.  Digital Calibration of Nonlinear Memory Errors in Sigma–Delta Modulators , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[19]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[20]  Xiaoqing Wen,et al.  VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon) , 2006 .

[21]  Jacob A. Abraham,et al.  Parallel Loopback Test of Mixed-Signal Circuits , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[22]  Soon-Jyh Chang,et al.  Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique , 2009, 2009 Asian Test Symposium.

[23]  Kwang-Ting Cheng,et al.  Recent Advances in Analog, Mixed-Signal, and RF Testing , 2010, IPSJ Trans. Syst. LSI Des. Methodol..

[24]  D. Richard Brown,et al.  Digital Background-Calibration Algorithm for “Split ADC” Architecture , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[25]  Kwang-Ting Cheng,et al.  A Built-in self-calibration scheme for pipelined ADCs , 2009, 2009 10th International Symposium on Quality Electronic Design.

[26]  Hae-Seung Lee,et al.  Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[27]  Ye Yi-zheng,et al.  Optimal Schemes for ADC BIST Based on Histogram , 2005, 14th Asian Test Symposium (ATS'05).

[28]  Florence Azaïs,et al.  Implementation of a linear histogram BIST for ADCs , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[29]  Kwang-Ting Cheng,et al.  Calibration-assisted production testing for digitally-calibrated ADCs , 2010, 2010 28th VLSI Test Symposium (VTS).

[30]  Robert W. Brodersen,et al.  Background ADC calibration in digital domain , 2008, 2008 IEEE Custom Integrated Circuits Conference.