Using ATPG for clock rules checking in complex scan designs

Structured Design-For-Testability (DFT) employs automated Design-Rules-Checking (DRC) to ensure a design is testable and test patterns can be produced using Automated Test Pattern Generation (ATPG). Central to DRC are ATPG-related clock rules. This paper defines a robust set of clock rules and their implementation for scan designs. It then extends clock-rule-violation detection beyond test requirements, which provides fast clock verification early in the design cycle, complementing the more complex and slower timing tools. Results on a large microprocessor design show the applicability of ATPG-based timing verification.

[1]  Prab Varma.  TDRC-a symbolic simulation based design for testability rules checker , 1990, Proceedings. International Test Conference 1990.

[2]  Randal E. Bryant,et al.  Verification of Arithmetic Circuits with Binary Moment Diagrams , 1995, 32nd Design Automation Conference.

[3]  Yasuhiko Sasaki,et al.  Lean integration: achieving a quantum leap in performance and cost of logic LSIs , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[4]  H. Al-Asaad,et al.  Design verification via simulation and automatic test pattern generation , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[5]  R. G. Bennetts,et al.  Design of testable logic circuits , 1984 .

[6]  Malgorzata Marek-Sadowska,et al.  Perturb and simplify: multi-level boolean network optimizer , 1994, ICCAD.

[7]  Peter Lidén,et al.  Switch-level modeling of transistor-level stuck-at faults , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[8]  Alfred L. Crouch,et al.  Testability features of the MC68060 microprocessor , 1994, Proceedings., International Test Conference.

[9]  Shi-Yu Huang,et al.  An ATPG-based framework for verifying sequential equivalence , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[10]  P. A. Subrahmanyam,et al.  Extracting RTL models from transistor netlists , 1995, ICCAD.

[11]  Randal E. Bryant,et al.  Automatic Clock Abstraction from Sequential Circuits , 1995, 32nd Design Automation Conference.

[12]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Masahiro Fujita,et al.  VERIFUL: VERIfication using FUnctional Learning , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[14]  Craig Hunter,et al.  Balancing structured and ad-hoc design for test: testing of the PowerPC 603 microprocessor , 1994, Proceedings., International Test Conference.

[15]  Premachandran R. Menon,et al.  Multi-level Logic Optimization By Implication Analysis , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[16]  E. J. McCluskey.  VLSI Design for Testability , 1984, 1984 Symposium on VLSI Technology. Digest of Technical Papers.

[17]  Peter Wohl,et al.  Test generation for ultra-large circuits using ATPG constraints and test-pattern templates , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[18]  Hugo De Man,et al.  Partial scan at the register-transfer level , 1993, Proceedings of IEEE International Test Conference - (ITC).

[19]  Sridhar Narayanan,et al.  Testability, debuggability, and manufacturability features of the UltraSPARC-I microprocessor , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[20]  P. A. Subrahmanyam,et al.  Extracting RTL models from transistor netlists , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[21]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[22]  Peter Wohl,et al.  Testing "untestable" faults in three-state circuits , 1996, Proceedings of 14th VLSI Test Symposium.

[23]  Anoosh Hosseini,et al.  Code generation and analysis for the functional verification of micro processors , 1996, DAC '96.