Harmonic distortion reduction in power inverters

The output voltage of PWM power inverters shows harmonic distortion due to several causes; the main ones are the modulation algorithm, nonlinearities due to the output filter, dead times, voltage drops across the switches and modulation of the dc bus voltage. The distortion is more evident when using low dc bus voltages. As a result, motors driven by these inverters have important torque pulsations. This work proposes to reduce the distortion produced by dead times and voltage drops across the switches, using a simple algorithm that recalculates the width of each PWM pulse, preserving the ideal area. The algorithm takes advantage of the fact that the dead times are not always necessary, but only when the load current changes its sign. By simulation, the THD was reduced from 18% to 0.29% in a single-phase inverter. The proposed algorithm only needs products and sums, so it is suitable for being implemented on a DSP with low processing load. Experimental results were obtained from a non-optimized laboratory prototype, showing a reduction of the THD from 17.9% to 0.59%.