PCI-express based high-speed readout for the BelleII DAQ Upgrade.

Belle II is a new generation B-factory experiment, dedicated to explore the new physics beyond the Standard Model of elementary particles at the flavor sector. Belle II has started data-taking since April, 2018, with a synchronous data acquisition (DAQ) system based on a pipelined trigger flow control. The Belle II DAQ system is designed to handle 30 kHz trigger rate with about 1% dead time under the raw event size more than 1 MB. It has been proved that the DAQ system is reliable and the overall data-taking efficiency has reached to 84.2% during the run period of Jan. 2020 - Jun. 2020. It is a big challenge to maintain the DAQ stability in the term of 10 years operation with current readout system, meanwhile, the readout system also becoming a bottleneck for providing higher speed data transmission. A solution of PCI-express based readout module with data throughput as high as 100 Gb/s, was adopted for the upgrade of Belle II DAQ system. We focus on in particular the design of firmware and software based on this new generation of readout board called PCIe40 with an Altera Arria 10 field-programmable gate array (FPGA) chip. 48 GBT (GigaBit Transceiver) serial links, PCI-express hard IP based DMA architecture, interface of Timing and Trigger Distribution (TTD) system, as well as the slow control system are designed for integrating with current Belle II DAQ system. This paper describes the performance accomplished during the data readout and slow control tests done with a pocket Belle II DAQ, as well as another demonstration test performed by using on-site Front-End Electronics (FEE), specifically involve Belle II TOP and KLM sub-detectors.

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