Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary

In this paper we present a new technique to speed up the effect-cause defect diagnosis by using a dictionary of very small size. In the proposed method, a dictionary of small size is used to reduce the number of events (gate evaluations) during the simulation of failing patterns and also a procedure to select a subset of passing patterns for simulation. Although the dictionary size is smaller, experimental results show speed up of effect-cause diagnosis by up to 156times. Experimental results from industrial designs validate the effectiveness of the proposed method.

[1]  Malgorzata Marek-Sadowska,et al.  An efficient and effective methodology on the multiple fault diagnosis , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[2]  Sudhakar M. Reddy,et al.  On methods to improve location based logic diagnosis , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[3]  Vamsi Boppana,et al.  Full fault dictionary storage based on labeled tree encoding , 1996, Proceedings of 14th VLSI Test Symposium.

[4]  M. Ray Mercer,et al.  Using logic models to predict the detection behavior of statistical timing defects , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[5]  Irith Pomeranz,et al.  On the generation of small dictionaries for fault location , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[6]  T. Larrabee.  Creating Small Fault Dictionaries , 1998 .

[7]  Srikanth Venkataraman,et al.  POIROT: a logic fault diagnosis tool and its applications , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[8]  Tracy Larrabee,et al.  Multiplets, models, and the search for meaning: improving per-test fault diagnosis , 2002, Proceedings. International Test Conference.

[9]  Tracy Larrabee,et al.  Creating small fault dictionaries [logic circuit fault diagnosis] , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Irith Pomeranz,et al.  Dominance based analysis for large volume production fail diagnosis , 2006, 24th IEEE VLSI Test Symposium.

[11]  Melvin A. Breuer,et al.  Fault Diagnosis Based on Effect-Cause Analysis: An Introduction , 1980, 17th Design Automation Conference.

[12]  Leendert M. Huisman,et al.  Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[13]  J.A. Waicukauski,et al.  Failure diagnosis of structured VLSI , 1989, IEEE Design & Test of Computers.