Low-Frequency Noise and Offset Rejection in DC-Coupled Neural Amplifiers: A Review and Digitally-Assisted Design Tutorial

We review integrated circuits for low-frequency noise and offset rejection as a motivation for the presented digitally-assisted neural amplifier design methodology. Conventional AC-coupled neural amplifiers inherently reject input DC offset but have key limitations in area, linearity, DC drift, and spectral accuracy. Their chopper stabilization reduces low-frequency intrinsic noise at the cost of degraded area, input impedance and design complexity. DC-coupled implementations with digital high-pass filtering yield improved area, linearity, drift, and spectral accuracy and are inherently suitable for simple chopper stabilization. As a design example, a 56-channel 0.13 <inline-formula><tex-math notation="LaTeX">$\mu\text{m}$</tex-math></inline-formula> CMOS intracranial EEG interface is presented. DC offset of up to <inline-formula><tex-math notation="LaTeX">$\pm$</tex-math></inline-formula>50 mV is rejected by a digital low-pass filter and a 16-bit delta-sigma DAC feeding back into the folding node of a folded-cascode LNA with CMRR of 65 dB. A bank of seven column-parallel fully differential SAR ADCs with ENOB of 6.6 are shared among 56 channels resulting in 0.018 <inline-formula><tex-math notation="LaTeX">$\text{mm}^{2}$</tex-math></inline-formula> effective channel area. Compensation-free direct input chopping yields integrated input-referred noise of 4.2 <inline-formula><tex-math notation="LaTeX">$\mu V_{\mathrm{rms}}$</tex-math></inline-formula> over the bandwidth of 1 Hz to 1 kHz. The 8.7 <inline-formula><tex-math notation="LaTeX">$\text{mm}^{2}$</tex-math></inline-formula> chip dissipating 1.07 mW has been validated <italic>in vivo</italic> in online intracranial EEG monitoring in freely moving rats.