Hardware-in-the-loop evolution of a 3-bit multiplier

In this paper, we focus on evolving a 3-bit multiplier from scratch. This method assume a dual-redundant FPGA system whereby the faulty FPGA undergoes evolution to recover its functionality, while the redundant FPGA maintains proper functionality during an evolution of the faulty FPGA. After the fault is detected, redundancy is lost for a short period of time and restored. The multiplier design is purely combinational, so that no feedbacks are allowed and can potentially take up to 48 LUTs. ECJ a Java-based evolutionary computation and genetic programming system is used for task like decoding.

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