FPGA acceleration of semantic tree reasoning algorithms

We design of a hardware unit to accelerate common-sense reasoning algorithms.The FPGA-based platform reduces significantly the execution times.Scalability is assured by means of a smart data mapping strategy. Semantic trees are a particular type of trees widely used in the representation of the concepts and their relations. Therefore, a computational model of the reality can be built and processed by Artificial Intelligence algorithms to infer knowledge, make decisions, etc. In this work, the design of a hardware component to accelerate reasoning operations on semantic trees by means of an FPGA based platform is presented. The target application is common-sense reasoning where marker-passing algorithms work on semantic tree structures; the core of the Scone Knowledge-Based system.On top of the functionality to be implemented, a strategy to deal with the implementation in reconfigurable hardware of dynamic and recursive data structures has been envisioned. Since lists, graphs or trees are the cornerstone in the modelling of computer friendly solutions for complex problems; this proposal contributes to reduce the breach between the software and silicon domains.As a result, an optimized micro-architecture of an FPGA accelerator for marker-passer algorithms integrated into a heterogeneous computing platform, and a smart data mapping procedure have been delivered. The design has been prototyped on a Xilinx ML507 board and compared to an equivalent software implementation, showing a significant reduction in execution times.

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