NOrec: streamlining STM by abolishing ownership records

Drawing inspiration from several previous projects, we present an ownership-record-free software transactional memory (STM) system that combines extremely low overhead with unusually clean semantics. While unlikely to scale to hundreds of active threads, this "NOrec" system offers many appealing features: very low fast-path latency--as low as any system we know of that admits concurrent updates; publication and privatization safety; livelock freedom; a small, constant amount of global metadata, and full compatibility with existing data structure layouts; no false conflicts due to hash collisions; compatibility with both managed and unmanaged languages, and both static and dynamic compilation; and easy acccommodation of closed nesting, inevitable (irrevocable) transactions, and starvation avoidance mechanisms. To the best of our knowledge, no extant STM system combines this set of features. While transactional memory for processors with hundreds of cores is likely to require hardware support, software implementations will be required for backward compatibility with current and near-future processors with 2--64 cores, as well as for fall-back in future machines when hardware resources are exhausted. Our experience suggests that NOrec may be an ideal candidate for such a software system. We also observe that it has considerable appeal for use within the operating system, and in systems that require both closed nesting and publication safety.

[1]  Chen Ding,et al.  Software behavior oriented parallelization , 2007, PLDI '07.

[2]  Christoph Lameter,et al.  Effective Synchronization on Linux/NUMA Systems , 2005 .

[3]  Nir Shavit,et al.  Transactional Mutex Locks , 2010, Euro-Par.

[4]  Antony L. Hosking,et al.  Nested transactional memory: Model and architecture sketches , 2006, Sci. Comput. Program..

[5]  Luke Dalessandro Michael,et al.  Strong Isolation is a Weak Idea , 2009 .

[6]  Mark Moir,et al.  PhTM: Phased Transactional Memory , 2007 .

[7]  Adam Welc,et al.  Practical weak-atomicity semantics for java stm , 2008, SPAA '08.

[8]  Marek Olszewski,et al.  JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory , 2007, 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007).

[9]  Rachid Guerraoui,et al.  On the correctness of transactional memory , 2008, PPoPP.

[10]  Michael F. Spear,et al.  A comprehensive strategy for contention management in software transactional memory , 2009, PPoPP '09.

[11]  Kunle Olukotun,et al.  STAMP: Stanford Transactional Applications for Multi-Processing , 2008, 2008 IEEE International Symposium on Workload Characterization.

[12]  Torvald Riegel,et al.  Time-based transactional memory with scalable time bases , 2007, SPAA '07.

[13]  Ali-Reza Adl-Tabatabai,et al.  McRT-Malloc: a scalable transactional memory allocator , 2006, ISMM '06.

[14]  Maged M. Michael,et al.  RingSTM: scalable transactions with a single atomic instruction , 2008, SPAA '08.

[15]  Yossi Lev Brown PhTM : Phased Transactional Memory ∗ , 2007 .

[16]  Victor Luchangco,et al.  Anatomy of a Scalable Software Transactional Memory , 2009 .

[17]  Martín Abadi,et al.  Semantics of transactional memory and automatic mutual exclusion , 2011, TOPL.

[18]  Torvald Riegel,et al.  Dynamic performance tuning of word-based software transactional memory , 2008, PPoPP.

[19]  Jeremy Manson,et al.  The Java memory model , 2005, POPL '05.

[20]  Hans-Juergen Boehm,et al.  Foundations of the C++ concurrency memory model , 2008, PLDI '08.

[21]  James R. Larus,et al.  Transactional Memory (Synthesis Lectures on Computer Architecture) , 2007 .

[22]  Michael F. Spear,et al.  Scalable Techniques for Transparent Privatization in Software Transactional Memory , 2008, 2008 37th International Conference on Parallel Processing.

[23]  Milo M. K. Martin,et al.  Subtleties of transactional memory atomicity semantics , 2006, IEEE Computer Architecture Letters.

[24]  Keir Fraser,et al.  Practical lock-freedom , 2003 .

[25]  Michael F. Spear,et al.  Ordering-Based Semantics for Software Transactional Memory , 2008, OPODIS.

[26]  Mark Moir,et al.  Hybrid transactional memory , 2006, ASPLOS XII.

[27]  Marc Tremblay,et al.  Rock: A High-Performance Sparc CMT Processor , 2009, IEEE Micro.

[28]  Nir Shavit,et al.  Transactional Locking II , 2006, DISC.

[29]  David Eisenstat,et al.  Lowering the Overhead of Software Transactional Memory , 2006 .

[30]  Bratin Saha,et al.  Code Generation and Optimization for Transactional Memory Constructs in an Unmanaged Language , 2007, International Symposium on Code Generation and Optimization (CGO'07).

[31]  Keir Fraser,et al.  Revocable locks for non-blocking programming , 2005, PPOPP.

[32]  Michael F. Spear,et al.  Privatization techniques for software transactional memory , 2007, PODC '07.

[33]  Mark Moir,et al.  Fast, Long-Lived Renaming Improved and Simplified , 1996, WDAG.

[34]  Jonathan Walpole,et al.  Exploiting deferred destruction: an analysis of read-copy-update techniques in operating system kernels , 2004 .

[35]  Dan Grossman,et al.  What do high-level memory models mean for transactions? , 2006, MSPC '06.

[36]  Mark Moir,et al.  Early experience with a commercial hardware transactional memory implementation , 2009, ASPLOS.