Adaptive gain, equalization, and wavelength stabilization techniques for silicon photonic microring resonator-based optical receivers

Interconnect architectures based on high-Q silicon photonic microring resonator devices offer a promising solution to address the dramatic increase in datacenter I/O bandwidth demands due to their ability to realize wavelength-division multiplexing (WDM) in a compact and energy efficient manner. However, challenges exist in realizing efficient receivers for these systems due to varying per-channel link budgets, sensitivity requirements, and ring resonance wavelength shifts. This paper reports on adaptive optical receiver design techniques which address these issues and have been demonstrated in two hybrid-integrated prototypes based on microring drop filters and waveguide photodetectors implemented in a 130nm SOI process and high-speed optical front-ends designed in 65nm CMOS. A 10Gb/s powerscalable architecture employs supply voltage scaling of a three inverter-stage transimpedance amplifier (TIA) that is adapted with an eye-monitor control loop to yield the necessary sensitivity for a given channel. As reduction of TIA input-referred noise is more critical at higher data rates, a 25Gb/s design utilizes a large input-stage feedback resistor TIA cascaded with a continuous-time linear equalizer (CTLE) that compensates for the increased input pole. When tested with a waveguide Ge PD with 0.45A/W responsivity, this topology achieves 25Gb/s operation with -8.2dBm sensitivity at a BER=10-12. In order to address microring drop filters sensitivity to fabrication tolerances and thermal variations, efficient wavelength-stabilization control loops are necessary. A peak-power-based monitoring loop which locks the drop filter to the input wavelength, while achieving compatibility with the high-speed TIA offset-correction feedback loop is implemented with a 0.7nm tuning range at 43μW/GHz efficiency.

[1]  Cheng Li,et al.  22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[2]  Binhao Wang,et al.  Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS , 2014, IEEE Journal of Solid-State Circuits.

[3]  Chen Sun,et al.  Addressing link-level design tradeoffs for integrated photonic interconnects , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[4]  Guo-Qiang Lo,et al.  High-Speed Silicon Modulator With Slow-Wave Electrodes and Fully Independent Differential Drive , 2014, Journal of Lightwave Technology.

[5]  Ashok V. Krishnamoorthy,et al.  A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process , 2012, IEEE Journal of Solid-State Circuits.

[6]  Ashok V. Krishnamoorthy,et al.  10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS , 2012, IEEE Journal of Solid-State Circuits.

[7]  P. Gothoskar,et al.  Silicon Photonic Modulator Based on a MOS-Capacitor and a CMOS Driver , 2014, 2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS).

[8]  Dan Li,et al.  A Low-Noise Design Technique for High-Speed CMOS Optical Receivers , 2014, IEEE Journal of Solid-State Circuits.

[9]  Alexander V. Rylyakov,et al.  25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based optical links in 90nm CMOS , 2012, 2012 IEEE International Solid-State Circuits Conference.

[10]  Yang Liu,et al.  22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.