A 288-kb pseudostatic RAM with high density and ease of use has been fabricated using polycide-gate n-well CMOS technology. For high speed and low power dissipation, a half-V/SUB cc/ precharging scheme, with CMOS back biased to V/SUB BB/, was used. For easier use, an address transition detector, plus auto-refresh and self-refresh, were adopted. Organized as 32K/spl times/9 bits, the RAM occupies an area of 55 mm/SUP 2/ and has a cell size of 6.8/spl times/13.6 /spl mu/m/SUP 2/, which was achieved using the 2-/spl mu/m design rule. A typical address access time is 125 ns, and the operating current is 60 mA at a 125-ns cycle time. Standby power is 2 mA.
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