Thin-layer silicon-on-insulator high-voltage PMOS device and application

We present a thin-layer silicon-on-insulator (SOI) high-voltage PMOS device structure and measured performance characteristics. The all-implanted device structure supports voltage by multi-dimensional depletion from a combination of implanted surface pn junctions and MOS capacitor structures formed with multi-level dielectric deposition and metallization. A graded-doped body region has been optimized for application voltages from 100-600 V, and the structure has been evaluated in applications including high-voltage level shifting, low-dissipation bias networks, and high-voltage high-frequency class AB power output stages. The integrated high-voltage PMOS device structure enables low-power, high voltage, and high-speed complementary circuit topologies to be realized in a thin-layer SOI process flow, improving circuit efficiency and expanding the application base for thin-layer technology.

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