Transient current testing of dynamic CMOS circuits

We propose methods for testing dynamic CMOS circuits using the transient power supply current, i/sub DDT/. The methods are based on setting the primary inputs of the circuit under test, switching the clock signal and monitoring i/sub DDT/. We target resistive open defects that can either cause the circuit to fail, or introduce unacceptable delay and hence result in degraded circuit performance. Results of fault simulation of domino CMOS circuits show a high rate of detection for resistive open faults that cannot be otherwise detected using traditional voltage or I/sub DDQ/ testing. We also show that by using a normalization procedure, the defects can be detected with a single threshold setup in the presence of leakage and process variations.

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