Semiconductor memory device and write latency control method thereof

A semiconductor memory device capable of improving common bus efficiency is disclosed. The device comprises an address shifting circuit for delaying an address by an n+m number of clock cycles in response to a clock signal, a control signal generating circuit for combining a column address strobe (CAS) latency of n-value and one of first and second operation signals to generate a control signal, and a switching circuit for outputting the address delayed by the n+m number of clock cycles output from the address shifting circuit in response to the control signal. The first operation signal indicates that the n-value of the CAS latency is less than a predetermined value and write latency is fixed. The second operation signal indicates that the n-value of the CAS latency is equal to or greater than the predetermined value and the write latency is variable.