Optimization of the thermal reliability of a four-tier die-stacked SiP structure using finite element analysis and the Taguchi method

Abstract We used finite element analysis (FEA) and the Taguchi method to investigate the reliability of a four-tier die-stacked system-in-package (SiP) structure and to achieve the optimal design of the SiP structure under thermal cycling. A finite element model of a four-tier die-stacked SiP structure was developed to simulate the thermal stress distribution in the stacked die during the thermal cycling test. Scanning electron microscopy (SEM) was used to observe the failure sites of the SiP structure. The results show that the thermal stress is concentrated in the top die and that the maximum thermal stress occurs at the outmost four corners of the bottom of the top die. A micro-crack appears in the top die, and the crack starts from the bottom of the die close to the corner of die 4. Nine geometric parameters of the SiP structure were chosen as the variable factors, and the volume-averaged maximum thermal stress Δ σ max was chosen as the quality factor. An L12(29) orthogonal array was applied in a Taguchi experiment to estimate the effects of the nine factors and to reveal the optimal design of a four-tier die-stacked SiP structure based on the results of the thermal cycling test. The thickness of the top die has an important effect on the reliability; more than 21.2% of the volume-averaged maximum thermal stress is reduced using the optimal design.

[1]  Burak Birgören,et al.  Design optimization of cutting parameters when turning hardened AISI 4140 steel (63 HRC) with Al2O3 + TiCN mixed ceramic tool , 2007 .

[2]  Po-Chih Pan,et al.  Dielectric Characterization of Ultra-Thin Low-Loss Build-Up Substrate for System-in-Package (SiP) Modules , 2015, IEEE Transactions on Microwave Theory and Techniques.

[3]  E. Yamada,et al.  Prediction of board level reliability of drop test for system-in-package , 2008, 2008 IEEE 9th VLSI Packaging Workshop of Japan.

[4]  G. Q. Zhang,et al.  Multi-physics modeling in virtual prototyping of electronic packages--combined thermal, thermo-mechanical and vapor pressure modeling , 2004, Microelectron. Reliab..

[5]  K. M. Chen Impact of packaging materials on reliability test for low-K wire bond-stacked flip chip CSP , 2009 .

[6]  Yi-Shao Lai,et al.  Optimization of Thermomechanical Reliability of Board-level Package-on-Package Stacking Assembly , 2006, IEEE Transactions on Components and Packaging Technologies.

[7]  Sulaiman Hasan,et al.  Analyses of surface roughness by turning process using Taguchi method , 2007 .

[8]  Rong-Sheng Chen,et al.  Interval optimal design of 3-D TSV stacked chips package reliability by using the genetic algorithm method , 2014, Microelectron. Reliab..

[9]  Jinsu Kim,et al.  Studies on the Thermal Cycling Reliability of BGA System-in-Package (SiP) With an Embedded Die , 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[10]  Shaochen Chen,et al.  Packaging for microelectromechanical and nanoelectromechanical systems , 2003 .

[11]  Yasumitsu Orii,et al.  Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package , 2012 .

[12]  Kang Yong Lee,et al.  Application of a design of experiments approach to the reliability of a PBGA package , 2005 .

[13]  Liu Yang Numerical Simulation of Stress-strain and Life Prediction for Lead-free Solder Joints of PBGA Package , 2007 .

[14]  Xiaosong Ma,et al.  Fast reliability qualification of SiP products , 2009, Microelectron. Reliab..

[15]  Yong Liu,et al.  Modeling for reliability of ultra thin chips in a system in package , 2014, 2014 IEEE 64th Electronic Components and Technology Conference (ECTC).

[16]  C. Fung,et al.  Multi-response optimization in friction properties of PBT composites using Taguchi method and principle component analysis , 2005 .

[17]  Bin Li,et al.  Optimal Design for Vibration Reliability of Package-on-Package Assembly Using FEA and Taguchi Method , 2016, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[18]  Bin Zhou,et al.  Analysis of board level vibration reliability of PoP structure with underfill material , 2016, 2016 17th International Conference on Electronic Packaging Technology (ICEPT).

[19]  Sheng Liu,et al.  Behavior of delaminated plastic IC packages subjected to encapsulation cooling, moisture absorption, and wave soldering , 1995 .

[20]  Zhaowei Zhong,et al.  Recent advances in wire bonding, flip chip and lead-free solder for advanced microelectronics packaging , 2007 .

[21]  Su-Tsai Lu,et al.  Reliability and Flexibility of Ultra-Thin Chip-on-Flex (UTCOF) Interconnects With Anisotropic Conductive Adhesive (ACA) Joints , 2010, IEEE Transactions on Advanced Packaging.

[22]  Wei-Hua Lu,et al.  Influence of die-shift-distance of overhang dies on residual thermal shear stress in 5-chip SiP after EMC curing , 2016 .

[23]  Bahgat Sammakia,et al.  A Review of Recent Advances in Thermal Management in Three Dimensional Chip Stacks in Electronic Systems , 2011 .

[24]  Charles A. Harper,et al.  Handbook of materials and processes for electronics , 1970 .