Managing Temperature Effects in Nanoscale Adaptive Systems
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[1] I. Filanovsky,et al. Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits , 2001 .
[2] Freeman L. Rawson,et al. EnergyScale for IBM POWER6 microprocessor-based systems , 2007, IBM J. Res. Dev..
[3] Yuan Xie,et al. Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design , 2006, J. VLSI Signal Process..
[4] Paul Ampadu,et al. A Low-Power Safety Mode for Variation Tolerant Systems-on-Chip , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.
[5] G.M. Quenot,et al. A temperature and voltage measurement cell for VLSI circuits , 1991, Euro ASIC '91.
[6] Stephan Henzler,et al. In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations , 2007, IEEE Journal of Solid-State Circuits.
[7] Volkan Kursun,et al. Supply and Threshold Voltage Optimization for Temperature Variation Insensitive Circuit Performance: A Comparison , 2006, 2006 IEEE International SOC Conference.
[8] James Tschanz,et al. Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[9] Yehea I. Ismail,et al. On the Scaling of Temperature-Dependent Effects , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[10] Fred J. Pollack. New microarchitecture challenges in the coming generations of CMOS process technologies (keynote address)(abstract only) , 1999, MICRO.
[11] Narayanan Vijaykrishnan,et al. Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.
[12] Davide Pandini,et al. Maximization of layout printability/manufacturability by extreme layout regularity , 2007 .
[13] Johan H. Huijsing,et al. A low–cost high–accuracy CMOS smart temperature sensor , 1999 .
[14] Katherine Shu-Min Li,et al. Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement , 2009, 2009 Asia and South Pacific Design Automation Conference.
[15] Shohaib Aboobacker. RAZOR: circuit-level correction of timing errors for low-power operation , 2011 .
[16] D. A. Antoniadis,et al. Measurement and modeling of self-heating effects in SOI nMOSFETs , 1992, 1992 International Technical Digest on Electron Devices Meeting.
[17] David J. Frank,et al. Nanoscale CMOS , 1999, Proc. IEEE.
[18] G. Lemieux,et al. Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement , 2005, International Conference on Field Programmable Logic and Applications, 2005..
[19] Chun-Chi Chen,et al. A Time Domain Mixed-Mode Temperature Sensor with Digital Set-Point Programming , 2006, IEEE Custom Integrated Circuits Conference 2006.
[20] Eric MacDonald,et al. Robust Ultra-Low Power Subthreshold Logic Flip-Flop Design for Reconfigurable Architectures , 2006, 2006 IEEE International Conference on Reconfigurable Computing and FPGA's (ReConFig 2006).
[21] T. Rahal-Arabi,et al. On-die droop detector for analog sensing of power supply noise , 2004, IEEE Journal of Solid-State Circuits.
[22] Paul Ampadu,et al. Adaptive Delay Correction for Runtime Variation in Dynamic voltage Scaling Systems , 2008, J. Circuits Syst. Comput..
[23] David Blaauw,et al. Ultralow-voltage, minimum-energy CMOS , 2006, IBM J. Res. Dev..
[24] Trevor Mudge,et al. A self-tuning DVS processor using delay-error detection and correction , 2005, VLSIC 2005.
[25] Yu Hu,et al. Minimal skew clock embedding considering time variant temperature gradient , 2007, ISPD '07.
[26] Kaustav Banerjee,et al. A power-optimal repeater insertion methodology for global interconnects in nanometer designs , 2002 .
[27] P. Silverman,et al. The Intel Lithography Roadmap , 2002 .
[28] Puneet Gupta,et al. Design sensitivities to variability: extrapolations and assessments in nanometer VLSI , 2002, 15th Annual IEEE International ASIC/SOC Conference.
[29] Vyshnavi Suntharalingam,et al. Enhanced resolution for future fabrication , 2003 .
[30] Yu Cao,et al. Predictive Technology Model for Nano-CMOS Design Exploration , 2006, 2006 1st International Conference on Nano-Networks and Workshops.
[31] Masayuki Miyazaki,et al. An LSI system with locked in temperature insensitive state achieved by using body bias technique , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[32] Luca Benini,et al. Error control schemes for on-chip communication links: the energy-reliability tradeoff , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[33] Axel Jantsch,et al. A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).
[34] Partha Pratim Pande,et al. Testing Network-on-Chip Communication Fabrics , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[35] Mahmudur Rahman,et al. Concurrent optimization of process dependent variations in different circuit performance measures , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..
[36] David Blaauw,et al. An ultra low power 1V, 220nW temperature sensor for passive wireless applications , 2008, 2008 IEEE Custom Integrated Circuits Conference.
[37] Radu Marculescu,et al. On-Chip Stochastic Communication , 2003, DATE.
[38] Seda Ogrenci Memik,et al. Inversed Temperature Dependence aware clock skew scheduling for sequential circuits , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[39] Paul Ampadu,et al. Adaptive error control for reliable systems-on-chip , 2008, 2008 IEEE International Symposium on Circuits and Systems.
[40] Pingshan Wang,et al. Pulsed wave interconnect , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[41] T. Chen,et al. Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[42] Massoud Pedram,et al. Clock-gating and its application to low power design of sequential circuits , 2000 .
[43] O. Semenov,et al. Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits , 2006, IEEE Transactions on Device and Materials Reliability.
[44] Luca Benini,et al. Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.
[45] Balaram Sinharoy,et al. Design and implementation of the POWER5 microprocessor , 2004, Proceedings. 41st Design Automation Conference, 2004..
[46] Bo Fu,et al. Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.
[47] U. Ruckert,et al. Extending scaling theory by adequately considering velocity saturation , 2002, 15th Annual IEEE International ASIC/SOC Conference.
[48] Mark Anders,et al. A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects , 2006, 2006 IEEE International SOC Conference.
[49] Young-Hyun Jun,et al. CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control , 2007, Microelectron. J..
[50] Ali Dasdan,et al. Handling inverted temperature dependence in static timing analysis , 2006, TODE.
[51] Li Shang,et al. Dynamic voltage scaling with links for power optimization of interconnection networks , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..
[52] Paul Ampadu,et al. A Sensor System to Detect Positive and Negative Current-Temperature Dependences , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.
[53] Trevor Mudge,et al. Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads , 2002, ICCAD 2002.
[54] Jinjun Xiong,et al. Optimal Margin Computation for At-Speed Test , 2008, 2008 Design, Automation and Test in Europe.
[55] Diana Marculescu,et al. Variability-Aware Frequency Scaling in Multi-Clock Processors , 2008 .
[56] Poki Chen,et al. An accurate CMOS delay-line-based smart temperature sensor for low-power low-cost systems , 2006 .
[57] C. Hu,et al. MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltages , 1996 .
[58] Paul Ampadu,et al. Self-Adaptive System for Addressing Permanent Errors in On-Chip Interconnects , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[59] Matthias Bucher,et al. Compact modelling of ultra deep submicron CMOS devices , 2002 .
[60] Herming Chiueh,et al. A high–speed CMOS on–chip temperature sensor , 1999 .
[61] Johan H. Huijsing,et al. Micropower CMOS temperature sensor with digital output , 1996, IEEE J. Solid State Circuits.
[62] Eby G. Friedman,et al. Decoupling capacitors for multi-voltage power distribution systems , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[63] Vivek De,et al. Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors , 2002, VLSIC 2002.
[64] Luca Benini,et al. Analysis of error recovery schemes for networks on chips , 2005, IEEE Design & Test of Computers.
[65] Daniel J. Costello,et al. Error Control Coding, Second Edition , 2004 .
[66] Paul Ampadu,et al. A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits , 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
[67] J. L. Leray. Effects of atmospheric neutrons on devices, at sea level and in avionics embedded systems , 2007, Microelectron. Reliab..
[68] Manoj Sachdev,et al. Variation-Aware Adaptive Voltage Scaling System , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[69] F. Fang,et al. Hot Electron Effects and Saturation Velocities in Silicon Inversion Layers , 1970 .
[70] Bo Fu,et al. Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design , 2010, 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip.
[71] Volkan Kursun,et al. Dual Supply Voltages and Dual Clock Frequencies for Lower Clock Power and Suppressed Temperature-Gradient-Induced Clock Skew , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[72] Yu Cao,et al. Mapping statistical process variations toward circuit performance variability: an analytical modeling approach , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[73] Enrico Macii,et al. Implementation of a thermal management unit for canceling temperature-dependent clock skew variations , 2008, Integr..
[74] Partha Pratim Pande,et al. NoC Interconnect Yield Improvement Using Crosspoint Redundancy , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
[75] George Varghese,et al. Low-swing on-chip signaling techniques: effectiveness and robustness , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[76] Jan M. Rabaey,et al. Digital Integrated Circuits: A Design Perspective , 1995 .
[77] G. R. Srinivasan. Modeling the cosmic-ray-induced soft-error rate in integrated circuits: An overview , 1996, IBM J. Res. Dev..
[78] James D. Meindl,et al. Temperature variable supply voltage for power reduction , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.
[79] David F. Heidel,et al. Alpha-particle-induced upsets in advanced CMOS circuits and technology , 2008, IBM J. Res. Dev..
[80] O. Semenov,et al. CMOS IC technology scaling and its impact on burn-in , 2004, IEEE Transactions on Device and Materials Reliability.
[81] William V. Huott,et al. Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[82] N.Y.A. Shammas,et al. A comprehensive review of thermoelectric technology, micro-electrical and power generation properties , 2008, 2008 26th International Conference on Microelectronics.
[83] Volkan Kursun,et al. Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.
[84] A.P. Chandrakasan,et al. A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[85] Nagata Makoto,et al. On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications , 2007 .
[86] Pasi Liljeberg,et al. Analysis of forward error correction methods for nanoscale networks-on-chip , 2007, Nano-Net.
[87] R. D. Valentine,et al. The Intel Pentium M processor: Microarchitecture and performance , 2003 .
[88] Giovanni De Micheli,et al. A robust self-calibrating transmission scheme for on-chip networks , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[89] Enrico Macii,et al. Temperature-insensitive synthesis using multi-vt libraries , 2008, GLSVLSI '08.
[90] Malgorzata Marek-Sadowska,et al. Benefits and costs of power-gating technique , 2005, 2005 International Conference on Computer Design.
[91] Kevin J. Nowka,et al. A Dual-VDD Boosted Pulsed Bus Technique for Low Power and Low Leakage Operation , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.
[92] Alfred L. Crouch,et al. Separating temperature effects from ring-oscillator readings to measure true IR-drop on a chip , 2007, 2007 IEEE International Test Conference.
[93] Y. P. Varshni. Temperature dependence of the energy gap in semiconductors , 1967 .
[94] Isamu Hayashi,et al. An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design , 2006, IEICE Trans. Electron..
[95] X. Garros,et al. 75 nm damascene metal gate and high-k integration for advanced CMOS devices , 2002, Digest. International Electron Devices Meeting,.
[96] Russell Tessier,et al. Trading off reliability and power-consumption in ultra-low power systems , 2002, Proceedings International Symposium on Quality Electronic Design.
[97] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[98] C. Hu,et al. Modelling temperature effects of quarter micrometre MOSFETs in BSIM3v3 for circuit simulation , 1997 .
[99] Sachin S. Sapatnekar,et al. Temperature-aware routing in 3D ICs , 2006, Asia and South Pacific Conference on Design Automation, 2006..
[100] Wayne P. Burleson,et al. Collaborative sensing of on-chip wire temperatures using interconnect based ring oscillators , 2008, GLSVLSI '08.
[101] David Blaauw,et al. Analysis and mitigation of variability in subthreshold design , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..
[102] Chang-Chi Lee,et al. On the thermal stability margins of high-leakage current packaged devices , 2006, 2006 8th Electronics Packaging Technology Conference.
[103] Robin Wilson,et al. Timing analysis in presence of supply voltage and temperature variations , 2006, ISPD '06.
[104] Mani B. Srivastava,et al. A survey of techniques for energy efficient on-chip communication , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[105] Yehea I. Ismail,et al. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[106] Massoud Pedram,et al. Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits , 2005, IEICE Trans. Electron..
[107] Hector Sanchez,et al. A 2.2 W, 80 MHz superscalar RISC microprocessor , 1994 .
[108] Vladimir Stojanovic,et al. Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems , 1999, IEEE J. Solid State Circuits.
[109] David J. Frank,et al. Power-constrained CMOS scaling limits , 2002, IBM J. Res. Dev..
[110] Shantanu Dutt,et al. Methodologies for Tolerating Cell and Interconnect Faults in FPGAs , 1998, IEEE Trans. Computers.
[111] J. Black,et al. Electromigration—A brief survey and some recent results , 1969 .
[112] Ingemar Lundström,et al. Influence of carbon monoxide, water and oxygen on high temperature catalytic metal-oxide-silicon carbide structures , 1997 .
[113] Changhae Park,et al. Reversal of temperature dependence of integrated circuits operating at very low voltages , 1995, Proceedings of International Electron Devices Meeting.
[114] Stefan Rusu. Trends and challenges in VLSI technology scaling towards 100nm , 2001, Proceedings of the 27th European Solid-State Circuits Conference.
[115] Shahin Nazarian,et al. Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods , 2006, Proceedings of the IEEE.
[116] Hiroshi Iwai,et al. On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors , 2006 .
[117] Wen-Kuan Yeh,et al. Impact of SOI thickness on device performance and gate oxide reliability of Ni fully silicide metal-gate strained SOI MOSFET , 2011 .
[118] Kaustav Banerjee,et al. Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[119] A.P. Chandrakasan,et al. Ultra-dynamic Voltage scaling (UDVS) using sub-threshold operation and local Voltage dithering , 2006, IEEE Journal of Solid-State Circuits.
[120] M. F. Behar. Handbook of industrial temperature and humidity measurement and control , 1962 .
[121] Chin-Chung Tsai,et al. A time-to-digital-converter-based CMOS smart temperature sensor , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[122] Jie Wei,et al. Challenges in Cooling Design of CPU Packages for High-Performance Servers , 2008 .
[123] M. J. Irwin,et al. Adaptive error protection for energy efficiency , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).
[124] Chun-Chi Chen,et al. A Time-Domain Sub-Micro Watt Temperature Sensor With Digital Set-Point Programming , 2009, IEEE Sensors Journal.
[125] Kiyoo Itoh,et al. Supply voltage scaling for temperature insensitive CMOS circuit operation , 1998 .
[126] Atsushi Kurokawa,et al. Challenge: variability characterization and modeling for 65- to 90-nm processes , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..
[127] J. Huijsing,et al. A CMOS smart temperature sensor with a 3σ inaccuracy of ±0.1°C from -55°C to 125°C , 2005, IEEE J. Solid State Circuits.
[128] Saurabh Dighe,et al. Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[129] Kofi A. A. Makinwa,et al. A CMOS smart temperature sensor with a batch-calibrated inaccuracy of ±0.25°C (3σ) from −70°C to 130°C , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[130] Sudhakar Bobba,et al. IC power distribution challenges , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).
[131] R. Ramaswami,et al. Book Review: Design and Analysis of Fault-Tolerant Digital Systems , 1990 .
[132] M. Tuthill. A switched-current, switched-capacitor temperature sensor in 0.6-/spl mu/m CMOS , 1998 .
[133] Wayne P. Burleson,et al. Thermal Impacts on NoC Interconnects , 2007, First International Symposium on Networks-on-Chip (NOCS'07).
[134] Mahmut T. Kandemir,et al. Leakage Current: Moore's Law Meets Static Power , 2003, Computer.
[135] S. Rusu,et al. Trends and challenges in VLSI technology scaling towards 100 nm , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.
[136] Narayanan Vijaykrishnan,et al. On-chip Bus Thermal Analysis and Optimization , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[137] Naresh R. Shanbhag,et al. Coding for systern-on-chip networks: a unified framework , 2004, Proceedings. 41st Design Automation Conference, 2004..
[138] Bo Zhang,et al. A 0.52 ppm/°C high-order temperature-compensated voltage reference , 2009 .
[139] Robin Wilson,et al. Temperature- and Voltage-Aware Timing Analysis , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[140] Y.W. Li,et al. A 1.05 V 1.6 mW, 0.45 $^{\circ}$C 3 $\sigma$ Resolution $\Sigma\Delta$ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process , 2009, IEEE Journal of Solid-State Circuits.
[141] A.P. Chandrakasan,et al. Standby power reduction using dynamic voltage scaling and canary flip-flop structures , 2004, IEEE Journal of Solid-State Circuits.
[142] Niccolò Rinaldi,et al. On the modeling of the transient thermal behavior of semiconductor devices , 2001 .
[143] Sung-Mo Kang,et al. Temperature-Aware Placement for SOCs , 2006, Proceedings of the IEEE.
[144] Paul Ampadu,et al. Normal and Reverse Temperature Dependence in Variation-Tolerant Nanoscale Systems with High-k Dielectrics and Metal Gates , 2008, NanoNet.
[145] Eby G. Friedman,et al. Three-dimensional Integrated Circuit Design , 2008 .
[146] Paolo Prinetto,et al. Reliability in Application Specific Mesh-Based NoC Architectures , 2008, 2008 14th IEEE International On-Line Testing Symposium.
[147] A. R. Newton,et al. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .
[148] David Blaauw,et al. Reducing pipeline energy demands with local DVS and dynamic retiming , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).
[149] Pasi Liljeberg,et al. Online Reconfigurable Self-Timed Links for Fault Tolerant NoC , 2007, VLSI Design.
[150] Kaushik Roy,et al. Leakage Power Analysis and Reduction for Nanoscale Circuits , 2006, IEEE Micro.
[151] G. Ji,et al. Design and validation of a power supply noise reduction technique , 2003, Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).
[152] David Z. Pan,et al. TACO: temperature aware clock-tree optimization , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[153] J.L. Ayala,et al. A Nanowatt Smart Temperature Sensor for Dynamic Thermal Management , 2008, IEEE Sensors Journal.
[154] Bo Fu,et al. On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.
[155] L. T. Su,et al. Prediction and Measurement of Temperature Fields in Silicon-on-Insulator Electronic Circuits , 1995 .
[156] Nobuto Ono,et al. On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design , 2005, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..
[157] E. Nowak,et al. High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res And Dev , 2006 .
[158] Volkan Kursun,et al. Impact of temperature fluctuations on circuit characteristics in 180nm and 65nm CMOS technologies , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[159] Ping Keung Ko,et al. A MOSFET electron mobility model of wide temperature range (77 - 400 K) for IC simulation , 1997 .
[160] J. Krupka,et al. Measurements of Permittivity, Dielectric Loss Tangent, and Resistivity of Float-Zone Silicon at Microwave Frequencies , 2006, IEEE Transactions on Microwave Theory and Techniques.
[161] Kevin Skadron,et al. The need for a full-chip and package thermal model for thermally optimized IC designs , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..
[162] Yuan Taur,et al. Device scaling limits of Si MOSFETs and their application dependencies , 2001, Proc. IEEE.
[163] D. E. Burk,et al. MOSFET electron inversion layer mobilities-a physically based semi-empirical model for a wide temperature range , 1989 .
[164] P. Tadayon. Thermal Challenges During Microprocessor Testing 1 Thermal Challenges During Microprocessor Testing , 2000 .
[165] Kaushik Roy,et al. Robust subthreshold logic for ultra-low power operation , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[166] Juha Tuoriniemi,et al. Nuclear cooling and spin properties of rhodium down to picokelvin temperatures , 2000 .
[167] Himanshu Kaul,et al. A novel buffer circuit for energy efficient signaling in dual-VDD systems , 2005, ACM Great Lakes Symposium on VLSI.
[168] Sharad Malik,et al. Power-driven design of router microarchitectures in on-chip networks , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..
[169] Cecilia Metra,et al. Configurable Error Control Scheme for NoC Signal Integrity , 2007, 13th IEEE International On-Line Testing Symposium (IOLTS 2007).
[170] Volkan Kursun,et al. Voltage optimization for simultaneous energy efficiency and temperature variation resilience in CMOS circuits , 2007, Microelectron. J..
[171] Paul Ampadu,et al. Level shifter speed, power, and reliability trade-offs across normal and reverse temperature dependences , 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.
[172] J. T. Clemens,et al. Characterization of the electron mobility in the inverted <100> Si surface , 1979, 1979 International Electron Devices Meeting.
[173] Anantha Chandrakasan,et al. Optimal supply and threshold scaling for subthreshold CMOS circuits , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.
[174] H. Shichman,et al. Modeling and simulation of insulated-gate field-effect transistor switching circuits , 1968 .