Hardware support for dynamic scheduling in multiprocessor Operating System

In the present paper, we propose a mechanism to support dynamic task scheduling on multiprocessor systems, which assists the scheduler in efficiently and adaptively managing the platform resources. The main objective of this method is to maximize system resource utilization, by allocating available platform resources to a task based on the individual task characteristics and performance requirements.

[1]  Jeff S. Brantley,et al.  Contention-Aware Scheduling of Parallel Code for Heterogeneous Systems , 2010 .

[2]  Eduard Ayguadé,et al.  Transactional Memory: An Overview , 2007, IEEE Micro.

[3]  Klaus Helwig,et al.  High Speed Content Addressable Memory , 1996, ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference.

[4]  Hyesoon Kim,et al.  Qilin: Exploiting parallelism on heterogeneous multiprocessors with adaptive mapping , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[5]  Daniel Shelepov.  Scheduling on Heterogeneous Multicore Processors Using Architectural Signatures , 2008 .

[6]  K. Pagiamtzis,et al.  Content-addressable memory (CAM) circuits and architectures: a tutorial and survey , 2006, IEEE Journal of Solid-State Circuits.

[7]  Maurice Herlihy,et al.  Transactional Memory: Architectural Support For Lock-free Data Structures , 1993, Proceedings of the 20th Annual International Symposium on Computer Architecture.