VLSI implementation of image segmentation processor for brain MRI

In this paper we present VLSI implementation of an automatic segmentation algorithm for Magnetic Resonance Images (MRI) of brain. The FPGA architecture incorporates all the functional units to realize the algorithm. The hardware implementation for threshold based segmentation is proposed. The processor capabilities can be extended to compute volume of the brain MRI. The experimental signal analysis and the resource requirement of the target device are also presented here.

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